Block based camera updates and asynchronous displays

ABSTRACT

Systems, methods and computer readable mediums provide for displaying pixels asynchronously on a display, block-based camera updates, and event driven frame updates on an asynchronous display.

TECHNICAL FIELD

Embodiments generally relate to display technology, and moreparticularly, to block based camera updates and asynchronous displays.

BACKGROUND OF THE DESCRIPTION

Raster scanning is a process used for displaying an image. The processmay require all pixels in a frame to be updated, wherein the image isupdated one pixel at a time for every frame. Each row of pixels may bescanned from left to right and every row may be scanned from top tobottom. Using a frame rate of 30 frames per second may be good for humanperception, but when virtual reality, augmented reality, or gaming isadded, 30 frames per second may not be enough to control latency. Higherframe rates may help to mitigate latency, but typically utilize aconsiderable amount of power.

BRIEF DESCRIPTION OF THE DRAWINGS

The various advantages of the embodiments will become apparent to oneskilled in the art by reading the following specification and appendedclaims, and by referencing the following drawings, in which:

FIG. 1 is a block diagram illustrating a computer system configured toimplement one or more aspects of the embodiments described herein;

FIG. 2A-2D illustrate a parallel processor components, according to anembodiment;

FIGS. 3A-3B are block diagrams of graphics multiprocessors, according toembodiments;

FIG. 4A-4F illustrate an exemplary architecture in which a plurality ofGPUs are communicatively coupled to a plurality of multi-coreprocessors;

FIG. 5 illustrates a graphics processing pipeline, according to anembodiment;

FIG. 6A is a diagram illustrating a conventional raster scan process fordisplaying a frame on a display;

FIG. 6B is a block diagram illustrating an asynchronous process forupdating a frame on an asynchronous display according to an embodiment;

FIG. 7A is an exemplary block diagram for block based camera updatesaccording to an embodiment;

FIG. 7B is a flow diagram illustrating an exemplary method for blockbased camera updates according to an embodiment;

FIG. 7C is a flow diagram illustrating another exemplary method forblock based camera updates according to an embodiment;

FIG. 7D is a flow diagram illustrating an exemplary method fordetermining update regions for block based camera updates according toan embodiment;

FIG. 7E illustrates an updated block/region according to an embodiment;

FIG. 8 is a block diagram illustrating an exemplary gaming systemaccording to an embodiment;

FIG. 9 is a table illustrating exemplary events and their weightedvalues for event driven updates on an asynchronous display according toan embodiment;

FIG. 10 is a flow diagram illustrating an exemplary event driven processfor event driven updates on an asynchronous display according to anembodiment;

FIG. 11 is a block diagram of an example of a display with a localizedbacklight capability according to an embodiment;

FIG. 12A is a block diagram of an example of a data processing deviceaccording to an embodiment;

FIG. 12B is an illustration of an example of a distance determinationaccording to an embodiment;

FIG. 13 is a block diagram of an example of a layered displayarchitecture according to an embodiment;

FIG. 14 is a block diagram of an example of a display architecture thatincludes multiple display units according to an embodiment; and

FIG. 15 is a block diagram of an example of a cloud-assisted mediadelivery architecture according to an embodiment;

FIGS. 16-18 are block diagrams of an example of an overview of a dataprocessing system according to an embodiment;

FIG. 19 is a block diagram of an example of a graphics processing engineaccording to an embodiment;

FIGS. 20-22 are block diagrams of examples of execution units accordingto an embodiment;

FIG. 23 is a block diagram of an example of a graphics pipelineaccording to an embodiment;

FIGS. 24A-24B are block diagrams of examples of graphics pipelineprogramming according to an embodiment;

FIG. 25 is a block diagram of an example of a graphics softwarearchitecture according to an embodiment;

FIG. 26 is a block diagram of an example of an intellectual property(IP) core development system according to an embodiment; and

FIG. 27 is a block diagram of an example of a system on a chipintegrated circuit according to an embodiment.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth toprovide a more thorough understanding of the present invention. However,it will be apparent to one of skill in the art that the presentinvention may be practiced without one or more of these specificdetails. In other instances, well-known features have not been describedin order to avoid obscuring the present invention.

System Overview

FIG. 1 is a block diagram illustrating a computing system 100 configuredto implement one or more aspects of the embodiments described herein.The computing system 100 includes a processing subsystem 101 having oneor more processor(s) 102 and a system memory 104 communicating via aninterconnection path that may include a memory hub 105. The memory hub105 may be a separate component within a chipset component or may beintegrated within the one or more processor(s) 102. The memory hub 105couples with an I/O subsystem 111 via a communication link 106. The I/Osubsystem 111 includes an I/O hub 107 that can enable the computingsystem 100 to receive input from one or more input device(s) 108.Additionally, the I/O hub 107 can enable a display controller, which maybe included in the one or more processor(s) 102, to provide outputs toone or more display device(s) 110A. In one embodiment the one or moredisplay device(s) 110A coupled with the I/O hub 107 can include a local,internal, or embedded display device.

In one embodiment the processing subsystem 101 includes one or moreparallel processor(s) 112 coupled to memory hub 105 via a bus or othercommunication link 113. The communication link 113 may be one of anynumber of standards based communication link technologies or protocols,such as, but not limited to PCI Express, or may be a vendor specificcommunications interface or communications fabric. In one embodiment theone or more parallel processor(s) 112 form a computationally focusedparallel or vector processing system that an include a large number ofprocessing cores and/or processing clusters, such as a many integratedcore (MIC) processor. In one embodiment the one or more parallelprocessor(s) 112 form a graphics processing subsystem that can outputpixels to one of the one or more display device(s) 110A coupled via theI/O Hub 107. The one or more parallel processor(s) 112 can also includea display controller and display interface (not shown) to enable adirect connection to one or more display device(s) 110B.

Within the I/O subsystem 111, a system storage unit 114 can connect tothe I/O hub 107 to provide a storage mechanism for the computing system100. An I/O switch 116 can be used to provide an interface mechanism toenable connections between the I/O hub 107 and other components, such asa network adapter 118 and/or wireless network adapter 119 that may beintegrated into the platform, and various other devices that can beadded via one or more add-in device(s) 120. The network adapter 118 canbe an Ethernet adapter or another wired network adapter. The wirelessnetwork adapter 119 can include one or more of a Wi-Fi, Bluetooth, nearfield communication (NFC), or other network device that includes one ormore wireless radios.

The computing system 100 can include other components not explicitlyshown, including USB or other port connections, optical storage drives,video capture devices, and the like, may also be connected to the I/Ohub 107. Communication paths interconnecting the various components inFIG. 1 may be implemented using any suitable protocols, such as PCI(Peripheral Component Interconnect) based protocols (e.g., PCI-Express),or any other bus or point-to-point communication interfaces and/orprotocol(s), such as the NV-Link high-speed interconnect, orinterconnect protocols known in the art.

In one embodiment, the one or more parallel processor(s) 112 incorporatecircuitry optimized for graphics and video processing, including, forexample, video output circuitry, and constitutes a graphics processingunit (GPU). In another embodiment, the one or more parallel processor(s)112 incorporate circuitry optimized for general purpose processing,while preserving the underlying computational architecture, described ingreater detail herein. In yet another embodiment, components of thecomputing system 100 may be integrated with one or more other systemelements on a single integrated circuit. For example, the one or moreparallel processor(s), 112 memory hub 105, processor(s) 102, and I/O hub107 can be integrated into a system on chip (SoC) integrated circuit.Alternatively, the components of the computing system 100 can beintegrated into a single package to form a system in package (SIP)configuration. In one embodiment at least a portion of the components ofthe computing system 100 can be integrated into a multi-chip module(MCM), which can be interconnected with other multi-chip modules into amodular computing system.

It will be appreciated that the computing system 100 shown herein isillustrative and that variations and modifications are possible. Theconnection topology, including the number and arrangement of bridges,the number of processor(s) 102, and the number of parallel processor(s)112, may be modified as desired. For instance, in some embodiments,system memory 104 is connected to the processor(s) 102 directly ratherthan through a bridge, while other devices communicate with systemmemory 104 via the memory hub 105 and the processor(s) 102. In otheralternative topologies, the parallel processor(s) 112 are connected tothe I/O hub 107 or directly to one of the one or more processor(s) 102,rather than to the memory hub 105. In other embodiments, the I/O hub 107and memory hub 105 may be integrated into a single chip. Someembodiments may include two or more sets of processor(s) 102 attachedvia multiple sockets, which can couple with two or more instances of theparallel processor(s) 112.

Some of the particular components shown herein are optional and may notbe included in all implementations of the computing system 100. Forexample, any number of add-in cards or peripherals may be supported, orsome components may be eliminated. Furthermore, some architectures mayuse different terminology for components similar to those illustrated inFIG. 1. For example, the memory hub 105 may be referred to as aNorthbridge in some architectures, while the I/O hub 107 may be referredto as a Southbridge.

FIG. 2A illustrates a parallel processor 200, according to anembodiment. The various components of the parallel processor 200 may beimplemented using one or more integrated circuit devices, such asprogrammable processors, application specific integrated circuits(ASICs), or field programmable gate arrays (FPGA). The illustratedparallel processor 200 is a variant of the one or more parallelprocessor(s) 112 shown in FIG. 1, according to an embodiment.

In one embodiment the parallel processor 200 includes a parallelprocessing unit 202. The parallel processing unit includes an I/O unit204 that enables communication with other devices, including otherinstances of the parallel processing unit 202. The I/O unit 204 may bedirectly connected to other devices. In one embodiment the I/O unit 204connects with other devices via the use of a hub or switch interface,such as memory hub 105. The connections between the memory hub 105 andthe I/O unit 204 form a communication link 113. Within the parallelprocessing unit 202, the I/O unit 204 connects with a host interface 206and a memory crossbar 216, where the host interface 206 receivescommands directed to performing processing operations and the memorycrossbar 216 receives commands directed to performing memory operations.

When the host interface 206 receives a command buffer via the I/O unit204, the host interface 206 can direct work operations to perform thosecommands to a front end 208. In one embodiment the front end 208 coupleswith a scheduler 210, which is configured to distribute commands orother work items to a processing cluster array 212. In one embodimentthe scheduler 210 ensures that the processing cluster array 212 isproperly configured and in a valid state before tasks are distributed tothe processing clusters of the processing cluster array 212. In oneembodiment the scheduler 210 is implemented via firmware logic executingon a microcontroller. The microcontroller implemented scheduler 210 isconfigurable to perform complex scheduling and work distributionoperations at coarse and fine granularity, enabling rapid preemption andcontext switching of threads executing on the processing array 212. Inone embodiment, the host software can prove workloads for scheduling onthe processing array 212 via one of multiple graphics processingdoorbells. The workloads can then be automatically distributed acrossthe processing array 212 by the scheduler 210 logic within the schedulermicrocontroller.

The processing cluster array 212 can include up to “N” processingclusters (e.g., cluster 214A, cluster 214B, through cluster 214N). Eachcluster 214A-214N of the processing cluster array 212 can execute alarge number of concurrent threads. The scheduler 210 can allocate workto the clusters 214A-214N of the processing cluster array 212 usingvarious scheduling and/or work distribution algorithms, which may varydepending on the workload arising for each type of program orcomputation. The scheduling can be handled dynamically by the scheduler210, or can be assisted in part by compiler logic during compilation ofprogram logic configured for execution by the processing cluster array212. In one embodiment, different clusters 214A-214N of the processingcluster array 212 can be allocated for processing different types ofprograms or for performing different types of computations.

The processing cluster array 212 can be configured to perform varioustypes of parallel processing operations. In one embodiment theprocessing cluster array 212 is configured to perform general-purposeparallel compute operations. For example, the processing cluster array212 can include logic to execute processing tasks including filtering ofvideo and/or audio data, performing modeling operations, includingphysics operations, and performing data transformations.

In one embodiment the processing cluster array 212 is configured toperform parallel graphics processing operations. In embodiments in whichthe parallel processor 200 is configured to perform graphics processingoperations, the processing cluster array 212 can include additionallogic to support the execution of such graphics processing operations,including, but not limited to texture sampling logic to perform textureoperations, as well as tessellation logic and other vertex processinglogic. Additionally, the processing cluster array 212 can be configuredto execute graphics processing related shader programs such as, but notlimited to vertex shaders, tessellation shaders, geometry shaders, andpixel shaders. The parallel processing unit 202 can transfer data fromsystem memory via the I/O unit 204 for processing. During processing thetransferred data can be stored to on-chip memory (e.g., parallelprocessor memory 222) during processing, then written back to systemmemory.

In one embodiment, when the parallel processing unit 202 is used toperform graphics processing, the scheduler 210 can be configured todivide the processing workload into approximately equal sized tasks, tobetter enable distribution of the graphics processing operations tomultiple clusters 214A-214N of the processing cluster array 212. In someembodiments, portions of the processing cluster array 212 can beconfigured to perform different types of processing. For example a firstportion may be configured to perform vertex shading and topologygeneration, a second portion may be configured to perform tessellationand geometry shading, and a third portion may be configured to performpixel shading or other screen space operations, to produce a renderedimage for display. Intermediate data produced by one or more of theclusters 214A-214N may be stored in buffers to allow the intermediatedata to be transmitted between clusters 214A-214N for furtherprocessing.

During operation, the processing cluster array 212 can receiveprocessing tasks to be executed via the scheduler 210, which receivescommands defining processing tasks from front end 208. For graphicsprocessing operations, processing tasks can include indices of data tobe processed, e.g., surface (patch) data, primitive data, vertex data,and/or pixel data, as well as state parameters and commands defining howthe data is to be processed (e.g., what program is to be executed). Thescheduler 210 may be configured to fetch the indices corresponding tothe tasks or may receive the indices from the front end 208. The frontend 208 can be configured to ensure the processing cluster array 212 isconfigured to a valid state before the workload specified by incomingcommand buffers (e.g., batch-buffers, push buffers, etc.) is initiated.

Each of the one or more instances of the parallel processing unit 202can couple with parallel processor memory 222. The parallel processormemory 222 can be accessed via the memory crossbar 216, which canreceive memory requests from the processing cluster array 212 as well asthe I/O unit 204. The memory crossbar 216 can access the parallelprocessor memory 222 via a memory interface 218. The memory interface218 can include multiple partition units (e.g., partition unit 220A,partition unit 220B, through partition unit 220N) that can each coupleto a portion (e.g., memory unit) of parallel processor memory 222. Inone implementation the number of partition units 220A-220N is configuredto be equal to the number of memory units, such that a first partitionunit 220A has a corresponding first memory unit 224A, a second partitionunit 220B has a corresponding memory unit 224B, and an Nth partitionunit 220N has a corresponding Nth memory unit 224N. In otherembodiments, the number of partition units 220A-220N may not be equal tothe number of memory devices.

In various embodiments, the memory units 224A-224N can include varioustypes of memory devices, including dynamic random access memory (DRAM)or graphics random access memory, such as synchronous graphics randomaccess memory (SGRAM), including graphics double data rate (GDDR)memory. In one embodiment, the memory units 224A-224N may also include3D stacked memory, including but not limited to high bandwidth memory(HBM). Persons skilled in the art will appreciate that the specificimplementation of the memory units 224A-224N can vary, and can beselected from one of various conventional designs. Render targets, suchas frame buffers or texture maps may be stored across the memory units224A-224N, allowing partition units 220A-220N to write portions of eachrender target in parallel to efficiently use the available bandwidth ofparallel processor memory 222. In some embodiments, a local instance ofthe parallel processor memory 222 may be excluded in favor of a unifiedmemory design that utilizes system memory in conjunction with localcache memory.

In one embodiment, any one of the clusters 214A-214N of the processingcluster array 212 can process data that will be written to any of thememory units 224A-224N within parallel processor memory 222. The memorycrossbar 216 can be configured to transfer the output of each cluster214A-214N to any partition unit 220A-220N or to another cluster214A-214N, which can perform additional processing operations on theoutput. Each cluster 214A-214N can communicate with the memory interface218 through the memory crossbar 216 to read from or write to variousexternal memory devices. In one embodiment the memory crossbar 216 has aconnection to the memory interface 218 to communicate with the I/O unit204, as well as a connection to a local instance of the parallelprocessor memory 222, enabling the processing units within the differentprocessing clusters 214A-214N to communicate with system memory or othermemory that is not local to the parallel processing unit 202. In oneembodiment the memory crossbar 216 can use virtual channels to separatetraffic streams between the clusters 214A-214N and the partition units220A-220N.

While a single instance of the parallel processing unit 202 isillustrated within the parallel processor 200, any number of instancesof the parallel processing unit 202 can be included. For example,multiple instances of the parallel processing unit 202 can be providedon a single add-in card, or multiple add-in cards can be interconnected.The different instances of the parallel processing unit 202 can beconfigured to inter-operate even if the different instances havedifferent numbers of processing cores, different amounts of localparallel processor memory, and/or other configuration differences. Forexample and in one embodiment, some instances of the parallel processingunit 202 can include higher precision floating point units relative toother instances. Systems incorporating one or more instances of theparallel processing unit 202 or the parallel processor 200 can beimplemented in a variety of configurations and form factors, includingbut not limited to desktop, laptop, or handheld personal computers,servers, workstations, game consoles, and/or embedded systems.

FIG. 2B is a block diagram of a partition unit 220, according to anembodiment. In one embodiment the partition unit 220 is an instance ofone of the partition units 220A-220N of FIG. 2A. As illustrated, thepartition unit 220 includes an L2 cache 221, a frame buffer interface225, and a ROP 226 (raster operations unit). The L2 cache 221 is aread/write cache that is configured to perform load and store operationsreceived from the memory crossbar 216 and ROP 226. Read misses andurgent write-back requests are output by L2 cache 221 to frame bufferinterface 225 for processing. Updates can also be sent to the framebuffer via the frame buffer interface 225 for processing. In oneembodiment the frame buffer interface 225 interfaces with one of thememory units in parallel processor memory, such as the memory units224A-224N of FIG. 2 (e.g., within parallel processor memory 222).

In graphics applications, the ROP 226 is a processing unit that performsraster operations such as stencil, z test, blending, and the like. TheROP 226 then outputs processed graphics data that is stored in graphicsmemory. In some embodiments the ROP 226 includes compression logic tocompress depth or color data that is written to memory and decompressdepth or color data that is read from memory. The compression logic canbe lossless compression logic that makes use of one or more of multiplecompression algorithms. The type of compression that is performed by theROP 226 can vary based on the statistical characteristics of the data tobe compressed. For example, in one embodiment, delta color compressionis performed on depth and color data on a per-tile basis.

In some embodiments, the ROP 226 is included within each processingcluster (e.g., cluster 214A-214N of FIG. 2) instead of within thepartition unit 220. In such embodiment, read and write requests forpixel data are transmitted over the memory crossbar 216 instead of pixelfragment data. The processed graphics data may be displayed on a displaydevice, such as one of the one or more display device(s) 110 of FIG. 1,routed for further processing by the processor(s) 102, or routed forfurther processing by one of the processing entities within the parallelprocessor 200 of FIG. 2A.

FIG. 2C is a block diagram of a processing cluster 214 within a parallelprocessing unit, according to an embodiment. In one embodiment theprocessing cluster is an instance of one of the processing clusters214A-214N of FIG. 2. The processing cluster 214 can be configured toexecute many threads in parallel, where the term “thread” refers to aninstance of a particular program executing on a particular set of inputdata. In some embodiments, single-instruction, multiple-data (SIMD)instruction issue techniques are used to support parallel execution of alarge number of threads without providing multiple independentinstruction units. In other embodiments, single-instruction,multiple-thread (SIMT) techniques are used to support parallel executionof a large number of generally synchronized threads, using a commoninstruction unit configured to issue instructions to a set of processingengines within each one of the processing clusters. Unlike a SIMDexecution regime, where all processing engines typically executeidentical instructions, SIMT execution allows different threads to morereadily follow divergent execution paths through a given thread program.Persons skilled in the art will understand that a SIMD processing regimerepresents a functional subset of a SIMT processing regime.

Operation of the processing cluster 214 can be controlled via a pipelinemanager 232 that distributes processing tasks to SIMT parallelprocessors. The pipeline manager 232 receives instructions from thescheduler 210 of FIG. 2 and manages execution of those instructions viaa graphics multiprocessor 234 and/or a texture unit 236. The illustratedgraphics multiprocessor 234 is an exemplary instance of a SIMT parallelprocessor. However, various types of SIMT parallel processors ofdiffering architectures may be included within the processing cluster214. One or more instances of the graphics multiprocessor 234 can beincluded within a processing cluster 214. The graphics multiprocessor234 can process data and a data crossbar 240 can be used to distributethe processed data to one of multiple possible destinations, includingother shader units. The pipeline manager 232 can facilitate thedistribution of processed data by specifying destinations for processeddata to be distributed vis the data crossbar 240.

Each graphics multiprocessor 234 within the processing cluster 214 caninclude an identical set of functional execution logic (e.g., arithmeticlogic units, load-store units, etc.). The functional execution logic canbe configured in a pipelined manner in which new instructions can beissued before previous instructions are complete. The functionalexecution logic supports a variety of operations including integer andfloating point arithmetic, comparison operations, Boolean operations,bit-shifting, and computation of various algebraic functions. In oneembodiment the same functional-unit hardware can be leveraged to performdifferent operations and any combination of functional units may bepresent.

The instructions transmitted to the processing cluster 214 constitutes athread. A set of threads executing across the set of parallel processingengines is a thread group. A thread group executes the same program ondifferent input data. Each thread within a thread group can be assignedto a different processing engine within a graphics multiprocessor 234. Athread group may include fewer threads than the number of processingengines within the graphics multiprocessor 234. When a thread groupincludes fewer threads than the number of processing engines, one ormore of the processing engines may be idle during cycles in which thatthread group is being processed. A thread group may also include morethreads than the number of processing engines within the graphicsmultiprocessor 234. When the thread group includes more threads than thenumber of processing engines within the graphics multiprocessor 234processing can be performed over consecutive clock cycles. In oneembodiment multiple thread groups can be executed concurrently on agraphics multiprocessor 234.

In one embodiment the graphics multiprocessor 234 includes an internalcache memory to perform load and store operations. In one embodiment,the graphics multiprocessor 234 can forego an internal cache and use acache memory (e.g., L1 cache 308) within the processing cluster 214.Each graphics multiprocessor 234 also has access to L2 caches within thepartition units (e.g., partition units 220A-220N of FIG. 2) that areshared among all processing clusters 214 and may be used to transferdata between threads. The graphics multiprocessor 234 may also accessoff-chip global memory, which can include one or more of local parallelprocessor memory and/or system memory. Any memory external to theparallel processing unit 202 may be used as global memory. Embodimentsin which the processing cluster 214 includes multiple instances of thegraphics multiprocessor 234 can share common instructions and data,which may be stored in the L1 cache 308.

Each processing cluster 214 may include an MMU 245 (memory managementunit) that is configured to map virtual addresses into physicaladdresses. In other embodiments, one or more instances of the MMU 245may reside within the memory interface 218 of FIG. 2. The MMU 245includes a set of page table entries (PTEs) used to map a virtualaddress to a physical address of a tile (talk more about tiling) andoptionally a cache line index. The MMU 245 may include addresstranslation lookaside buffers (TLB) or caches that may reside within thegraphics multiprocessor 234 or the L1 cache or processing cluster 214.The physical address is processed to distribute surface data accesslocality to allow efficient request interleaving among partition units.The cache line index may be used to determine whether a request for acache line is a hit or miss.

In graphics and computing applications, a processing cluster 214 may beconfigured such that each graphics multiprocessor 234 is coupled to atexture unit 236 for performing texture mapping operations, e.g.,determining texture sample positions, reading texture data, andfiltering the texture data. Texture data is read from an internaltexture L1 cache (not shown) or in some embodiments from the L1 cachewithin graphics multiprocessor 234 and is fetched from an L2 cache,local parallel processor memory, or system memory, as needed. Eachgraphics multiprocessor 234 outputs processed tasks to the data crossbar240 to provide the processed task to another processing cluster 214 forfurther processing or to store the processed task in an L2 cache, localparallel processor memory, or system memory via the memory crossbar 216.A preROP 242 (pre-raster operations unit) is configured to receive datafrom graphics multiprocessor 234, direct data to ROP units, which may belocated with partition units as described herein (e.g., partition units220A-220N of FIG. 2). The preROP 242 unit can perform optimizations forcolor blending, organize pixel color data, and perform addresstranslations.

It will be appreciated that the core architecture described herein isillustrative and that variations and modifications are possible. Anynumber of processing units, e.g., graphics multiprocessor 234, textureunits 236, preROPs 242, etc., may be included within a processingcluster 214. Further, while only one processing cluster 214 is shown, aparallel processing unit as described herein may include any number ofinstances of the processing cluster 214. In one embodiment, eachprocessing cluster 214 can be configured to operate independently ofother processing clusters 214 using separate and distinct processingunits, L1 caches, etc.

FIG. 2D shows a graphics multiprocessor 234, according to oneembodiment. In such embodiment the graphics multiprocessor 234 coupleswith the pipeline manager 232 of the processing cluster 214. Thegraphics multiprocessor 234 has an execution pipeline including but notlimited to an instruction cache 252, an instruction unit 254, an addressmapping unit 256, a register file 258, one or more general purposegraphics processing unit (GPGPU) cores 262, and one or more load/storeunits 266. The GPGPU cores 262 and load/store units 266 are coupled withcache memory 272 and shared memory 270 via a memory and cacheinterconnect 268.

In one embodiment, the instruction cache 252 receives a stream ofinstructions to execute from the pipeline manager 232. The instructionsare cached in the instruction cache 252 and dispatched for execution bythe instruction unit 254. The instruction unit 254 can dispatchinstructions as thread groups (e.g., warps), with each thread of thethread group assigned to a different execution unit within GPGPU core262. An instruction can access any of a local, shared, or global addressspace by specifying an address within a unified address space. Theaddress mapping unit 256 can be used to translate addresses in theunified address space into a distinct memory address that can beaccessed by the load/store units 266.

The register file 258 provides a set of registers for the functionalunits of the graphics multiprocessor 324. The register file 258 providestemporary storage for operands connected to the data paths of thefunctional units (e.g., GPGPU cores 262, load/store units 266) of thegraphics multiprocessor 324. In one embodiment, the register file 258 isdivided between each of the functional units such that each functionalunit is allocated a dedicated portion of the register file 258. In oneembodiment, the register file 258 is divided between the different warpsbeing executed by the graphics multiprocessor 324.

The GPGPU cores 262 can each include floating point units (FPUs) and/orinteger arithmetic logic units (ALUs) that are used to executeinstructions of the graphics multiprocessor 324. The GPGPU cores 262 canbe similar in architecture or can differ in architecture, according toembodiments. For example and in one embodiment, a first portion of theGPGPU cores 262 include a single precision FPU and an integer ALU whilea second portion of the GPGPU cores include a double precision FPU. Inone embodiment the FPUs can implement the IEEE 754-2008 standard forfloating point arithmetic or enable variable precision floating pointarithmetic. The graphics multiprocessor 324 can additionally include oneor more fixed function or special function units to perform specificfunctions such as copy rectangle or pixel blending operations. In oneembodiment one or more of the GPGPU cores can also include fixed orspecial function logic.

In one embodiment the GPGPU cores 262 include SIMD logic capable ofperforming a single instruction on multiple sets of data. In oneembodiment GPGPU cores 262 can physically execute SIMD4, SIMD8, andSIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32instructions. The SIMD instructions for the GPGPU cores can be generatedat compile time by a shader compiler or automatically generated whenexecuting programs written and compiled for single program multiple data(SPMD) or SIMT architectures. Multiple threads of a program configuredfor the SIMT execution model can executed via a single SIMD instruction.For example and in one embodiment, eight SIMT threads that perform thesame or similar operations can be executed in parallel via a singleSIMD8 logic unit.

The memory and cache interconnect 268 is an interconnect network thatconnects each of the functional units of the graphics multiprocessor 324to the register file 258 and to the shared memory 270. In oneembodiment, the memory and cache interconnect 268 is a crossbarinterconnect that allows the load/store unit 266 to implement load andstore operations between the shared memory 270 and the register file258. The register file 258 can operate at the same frequency as theGPGPU cores 262, thus data transfer between the GPGPU cores 262 and theregister file 258 is very low latency. The shared memory 270 can be usedto enable communication between threads that execute on the functionalunits within the graphics multiprocessor 234. The cache memory 272 canbe used as a data cache for example, to cache texture data communicatedbetween the functional units and the texture unit 236. The shared memory270 can also be used as a program managed cached. Threads executing onthe GPGPU cores 262 can programmatically store data within the sharedmemory in addition to the automatically cached data that is storedwithin the cache memory 272.

FIGS. 3A-3B illustrate additional graphics multiprocessors, according toembodiments. The illustrated graphics multiprocessors 325, 350 arevariants of the graphics multiprocessor 234 of FIG. 2C. The illustratedgraphics multiprocessors 325, 350 can be configured as a streamingmultiprocessor (SM) capable of simultaneous execution of a large numberof execution threads.

FIG. 3A shows a graphics multiprocessor 325 according to an additionalembodiment. The graphics multiprocessor 325 includes multiple additionalinstances of execution resource units relative to the graphicsmultiprocessor 234 of FIG. 2D. For example, the graphics multiprocessor325 can include multiple instances of the instruction unit 332A-332B,register file 334A-334B, and texture unit(s) 344A-344B. The graphicsmultiprocessor 325 also includes multiple sets of graphics or computeexecution units (e.g., GPGPU core 336A-336B, GPGPU core 337A-337B, GPGPUcore 338A-338B) and multiple sets of load/store units 340A-340B. In oneembodiment the execution resource units have a common instruction cache330, texture and/or data cache memory 342, and shared memory 346.

The various components can communicate via an interconnect fabric 327.In one embodiment the interconnect fabric 327 includes one or morecrossbar switches to enable communication between the various componentsof the graphics multiprocessor 325. In one embodiment the interconnectfabric 327 is a separate, high-speed network fabric layer upon whicheach component of the graphics multiprocessor 325 is stacked. Thecomponents of the graphics multiprocessor 325 communicate with remotecomponents via the interconnect fabric 327. For example, the GPGPU cores336A-336B, 337A-337B, and 3378A-338B can each communicate with sharedmemory 346 via the interconnect fabric 327. The interconnect fabric 327can arbitrate communication within the graphics multiprocessor 325 toensure a fair bandwidth allocation between components.

FIG. 3B shows a graphics multiprocessor 350 according to an additionalembodiment. The graphics processor includes multiple sets of executionresources 356A-356D, where each set of execution resource includesmultiple instruction units, register files, GPGPU cores, and load storeunits, as illustrated in FIG. 2D and FIG. 3A. The execution resources356A-356D can work in concert with texture unit(s) 360A-360D for textureoperations, while sharing an instruction cache 354, and shared memory362. In one embodiment the execution resources 356A-356D can share aninstruction cache 354 and shared memory 362, as well as multipleinstances of a texture and/or data cache memory 358A-358B. The variouscomponents can communicate via an interconnect fabric 352 similar to theinterconnect fabric 327 of FIG. 3A.

Persons skilled in the art will understand that the architecturedescribed in FIGS. 1, 2A-2D, and 3A-3B are descriptive and not limitingas to the scope of the present embodiments. Thus, the techniquesdescribed herein may be implemented on any properly configuredprocessing unit, including, without limitation, one or more mobileapplication processors, one or more desktop or server central processingunits (CPUs) including multi-core CPUs, one or more parallel processingunits, such as the parallel processing unit 202 of FIG. 2, as well asone or more graphics processors or special purpose processing units,without departure from the scope of the embodiments described herein.

In some embodiments a parallel processor or GPGPU as described herein iscommunicatively coupled to host/processor cores to accelerate graphicsoperations, machine-learning operations, pattern analysis operations,and various general purpose GPU (GPGPU) functions. The GPU may becommunicatively coupled to the host processor/cores over a bus or otherinterconnect (e.g., a high speed interconnect such as PCIe or NVLink).In other embodiments, the GPU may be integrated on the same package orchip as the cores and communicatively coupled to the cores over aninternal processor bus/interconnect (i.e., internal to the package orchip). Regardless of the manner in which the GPU is connected, theprocessor cores may allocate work to the GPU in the form of sequences ofcommands/instructions contained in a work descriptor. The GPU then usesdedicated circuitry/logic for efficiently processing thesecommands/instructions.

Techniques for GPU to Host Processor Interconnection

FIG. 4A illustrates an exemplary architecture in which a plurality ofGPUs 410-413 are communicatively coupled to a plurality of multi-coreprocessors 405-406 over high-speed links 440-443 (e.g., buses,point-to-point interconnects, etc.). In one embodiment, the high-speedlinks 440-443 support a communication throughput of 4 GB/s, 30 GB/s, 80GB/s or higher, depending on the implementation. Various interconnectprotocols may be used including, but not limited to, PCIe 4.0 or 5.0 andNVLink 2.0. However, the underlying principles of the invention are notlimited to any particular communication protocol or throughput.

In addition, in one embodiment, two or more of the GPUs 410-413 areinterconnected over high-speed links 444-445, which may be implementedusing the same or different protocols/links than those used forhigh-speed links 440-443. Similarly, two or more of the multi-coreprocessors 405-406 may be connected over high speed link 433 which maybe symmetric multi-processor (SMP) buses operating at 20 GB/s, 30 GB/s,120 GB/s or higher. Alternatively, all communication between the varioussystem components shown in FIG. 4A may be accomplished using the sameprotocols/links (e.g., over a common interconnection fabric). Asmentioned, however, the underlying principles of the invention are notlimited to any particular type of interconnect technology.

In one embodiment, each multi-core processor 405-406 is communicativelycoupled to a processor memory 401-402, via memory interconnects 430-431,respectively, and each GPU 410-413 is communicatively coupled to GPUmemory 420-423 over GPU memory interconnects 450-453, respectively. Thememory interconnects 430-431 and 450-453 may utilize the same ordifferent memory access technologies. By way of example, and notlimitation, the processor memories 401-402 and GPU memories 420-423 maybe volatile memories such as dynamic random access memories (DRAMs)(including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5,GDDR6), or High Bandwidth Memory (HBM) and/or may be non-volatilememories such as 3D XPoint or Nano-Ram. In one embodiment, some portionof the memories may be volatile memory and another portion may benon-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

As described below, although the various processors 405-406 and GPUs410-413 may be physically coupled to a particular memory 401-402,420-423, respectively, a unified memory architecture may be implementedin which the same virtual system address space (also referred to as the“effective address” space) is distributed among all of the variousphysical memories. For example, processor memories 401-402 may eachcomprise 64 GB of the system memory address space and GPU memories420-423 may each comprise 32 GB of the system memory address space(resulting in a total of 256 GB addressable memory in this example).

FIG. 4B illustrates additional details for an interconnection between amulti-core processor 407 and a graphics acceleration module 446 inaccordance with one embodiment. The graphics acceleration module 446 mayinclude one or more GPU chips integrated on a line card which is coupledto the processor 407 via the high-speed link 440. Alternatively, thegraphics acceleration module 446 may be integrated on the same packageor chip as the processor 407.

The illustrated processor 407 includes a plurality of cores 460A-460D,each with a translation lookaside buffer 461A-461D and one or morecaches 462A-462D. The cores may include various other components forexecuting instructions and processing data which are not illustrated toavoid obscuring the underlying principles of the invention (e.g.,instruction fetch units, branch prediction units, decoders, executionunits, reorder buffers, etc.). The caches 462A-462D may comprise level 1(L1) and level 2 (L2) caches. In addition, one or more shared caches 426may be included in the caching hierarchy and shared by sets of the cores460A-460D. For example, one embodiment of the processor 407 includes 24cores, each with its own L1 cache, twelve shared L2 caches, and twelveshared L3 caches. In this embodiment, one of the L2 and L3 caches areshared by two adjacent cores. The processor 407 and the graphicsaccelerator integration module 446 connect with system memory 441, whichmay include processor memories 401-402

Coherency is maintained for data and instructions stored in the variouscaches 462A-462D, 456 and system memory 441 via inter-core communicationover a coherence bus 464. For example, each cache may have cachecoherency logic/circuitry associated therewith to communicate to overthe coherence bus 464 in response to detected reads or writes toparticular cache lines. In one implementation, a cache snooping protocolis implemented over the coherence bus 464 to snoop cache accesses. Cachesnooping/coherency techniques are well understood by those of skill inthe art and will not be described in detail here to avoid obscuring theunderlying principles of the invention.

In one embodiment, a proxy circuit 425 communicatively couples thegraphics acceleration module 446 to the coherence bus 464, allowing thegraphics acceleration module 446 to participate in the cache coherenceprotocol as a peer of the cores. In particular, an interface 435provides connectivity to the proxy circuit 425 over high-speed link 440(e.g., a PCIe bus, NVLink, etc.) and an interface 437 connects thegraphics acceleration module 446 to the link 440.

In one implementation, an accelerator integration circuit 436 providescache management, memory access, context management, and interruptmanagement services on behalf of a plurality of graphics processingengines 431, 432, N of the graphics acceleration module 446. Thegraphics processing engines 431, 432, N may each comprise a separategraphics processing unit (GPU). Alternatively, the graphics processingengines 431, 432, N may comprise different types of graphics processingengines within a GPU such as graphics execution units, media processingengines (e.g., video encoders/decoders), samplers, and blit engines. Inother words, the graphics acceleration module may be a GPU with aplurality of graphics processing engines 431-432, N or the graphicsprocessing engines 431-432, N may be individual GPUs integrated on acommon package, line card, or chip.

In one embodiment, the accelerator integration circuit 436 includes amemory management unit (MMU) 439 for performing various memorymanagement functions such as virtual-to-physical memory translations(also referred to as effective-to-real memory translations) and memoryaccess protocols for accessing system memory 441. The MMU 439 may alsoinclude a translation lookaside buffer (TLB) (not shown) for caching thevirtual/effective to physical/real address translations. In oneimplementation, a cache 438 stores commands and data for efficientaccess by the graphics processing engines 431-432, N. In one embodiment,the data stored in cache 438 and graphics memories 433-434, N is keptcoherent with the core caches 462A-462D, 456 and system memory 411. Asmentioned, this may be accomplished via proxy circuit 425 which takespart in the cache coherency mechanism on behalf of cache 438 andmemories 433-434, N (e.g., sending updates to the cache 438 related tomodifications/accesses of cache lines on processor caches 462A-462D, 456and receiving updates from the cache 438).

A set of registers 445 store context data for threads executed by thegraphics processing engines 431-432, N and a context management circuit448 manages the thread contexts. For example, the context managementcircuit 448 may perform save and restore operations to save and restorecontexts of the various threads during contexts switches (e.g., where afirst thread is saved and a second thread is stored so that the secondthread can be execute by a graphics processing engine). For example, ona context switch, the context management circuit 448 may store currentregister values to a designated region in memory (e.g., identified by acontext pointer). It may then restore the register values when returningto the context. In one embodiment, an interrupt management circuit 447receives and processes interrupts received from system devices.

In one implementation, virtual/effective addresses from a graphicsprocessing engine 431 are translated to real/physical addresses insystem memory 411 by the MMU 439. One embodiment of the acceleratorintegration circuit 436 supports multiple (e.g., 4, 8, 16) graphicsaccelerator modules 446 and/or other accelerator devices. The graphicsaccelerator module 446 may be dedicated to a single application executedon the processor 407 or may be shared between multiple applications. Inone embodiment, a virtualized graphics execution environment ispresented in which the resources of the graphics processing engines431-432, N are shared with multiple applications or virtual machines(VMs). The resources may be subdivided into “slices” which are allocatedto different VMs and/or applications based on the processingrequirements and priorities associated with the VMs and/or applications.

Thus, the accelerator integration circuit acts as a bridge to the systemfor the graphics acceleration module 446 and provides addresstranslation and system memory cache services. In addition, theaccelerator integration circuit 436 may provide virtualizationfacilities for the host processor to manage virtualization of thegraphics processing engines, interrupts, and memory management.

Because hardware resources of the graphics processing engines 431-432, Nare mapped explicitly to the real address space seen by the hostprocessor 407, any host processor can address these resources directlyusing an effective address value. One function of the acceleratorintegration circuit 436, in one embodiment, is the physical separationof the graphics processing engines 431-432, N so that they appear to thesystem as independent units.

As mentioned, in the illustrated embodiment, one or more graphicsmemories 433-434, M are coupled to each of the graphics processingengines 431-432, N, respectively. The graphics memories 433-434, M storeinstructions and data being processed by each of the graphics processingengines 431-432, N. The graphics memories 433-434, M may be volatilememories such as DRAMs (including stacked DRAMs), GDDR memory (e.g.,GDDR5, GDDR6), or HBM, and/or may be non-volatile memories such as 3DXPoint or Nano-Ram.

In one embodiment, to reduce data traffic over link 440, biasingtechniques are used to ensure that the data stored in graphics memories433-434, M is data which will be used most frequently by the graphicsprocessing engines 431-432, N and preferably not used by the cores460A-460D (at least not frequently). Similarly, the biasing mechanismattempts to keep data needed by the cores (and preferably not thegraphics processing engines 431-432, N) within the caches 462A-462D, 456of the cores and system memory 411.

FIG. 4C illustrates another embodiment in which the acceleratorintegration circuit 436 is integrated within the processor 407. In thisembodiment, the graphics processing engines 431-432, N communicatedirectly over the high-speed link 440 to the accelerator integrationcircuit 436 via interface 437 and interface 435 (which, again, may beutilize any form of bus or interface protocol). The acceleratorintegration circuit 436 may perform the same operations as thosedescribed with respect to FIG. 4B, but potentially at a higherthroughput given its close proximity to the coherency bus 462 and caches462A-462D, 426.

One embodiment supports different programming models including adedicated-process programming model (no graphics acceleration modulevirtualization) and shared programming models (with virtualization). Thelatter may include programming models which are controlled by theaccelerator integration circuit 436 and programming models which arecontrolled by the graphics acceleration module 446.

In one embodiment of the dedicated process model, graphics processingengines 431-432, N are dedicated to a single application or processunder a single operating system. The single application can funnel otherapplication requests to the graphics engines 431-432, N, providingvirtualization within a VM/partition.

In the dedicated-process programming models, the graphics processingengines 431-432, N, may be shared by multiple VM/application partitions.The shared models require a system hypervisor to virtualize the graphicsprocessing engines 431-432, N to allow access by each operating system.For single-partition systems without a hypervisor, the graphicsprocessing engines 431-432, N are owned by the operating system. In bothcases, the operating system can virtualize the graphics processingengines 431-432, N to provide access to each process or application.

For the shared programming model, the graphics acceleration module 446or an individual graphics processing engine 431-432, N selects a processelement using a process handle. In one embodiment, process elements arestored in system memory 411 and are addressable using the effectiveaddress to real address translation techniques described herein. Theprocess handle may be an implementation-specific value provided to thehost process when registering its context with the graphics processingengine 431-432, N (that is, calling system software to add the processelement to the process element linked list). The lower 16-bits of theprocess handle may be the offset of the process element within theprocess element linked list.

FIG. 4D illustrates an exemplary accelerator integration slice 490. Asused herein, a “slice” comprises a specified portion of the processingresources of the accelerator integration circuit 436. Applicationeffective address space 482 within system memory 411 stores processelements 483. In one embodiment, the process elements 483 are stored inresponse to GPU invocations 481 from applications 480 executed on theprocessor 407. A process element 483 contains the process state for thecorresponding application 480. A work descriptor (WD) 484 contained inthe process element 483 can be a single job requested by an applicationor may contain a pointer to a queue of jobs. In the latter case, the WD484 is a pointer to the job request queue in the application's addressspace 482.

The graphics acceleration module 446 and/or the individual graphicsprocessing engines 431-432, N can be shared by all or a subset of theprocesses in the system. Embodiments of the invention include aninfrastructure for setting up the process state and sending a WD 484 toa graphics acceleration module 446 to start a job in a virtualizedenvironment.

In one implementation, the dedicated-process programming model isimplementation-specific. In this model, a single process owns thegraphics acceleration module 446 or an individual graphics processingengine 431. Because the graphics acceleration module 446 is owned by asingle process, the hypervisor initializes the accelerator integrationcircuit 436 for the owning partition and the operating systeminitializes the accelerator integration circuit 436 for the owningprocess at the time when the graphics acceleration module 446 isassigned.

In operation, a WD fetch unit 491 in the accelerator integration slice490 fetches the next WD 484 which includes an indication of the work tobe done by one of the graphics processing engines of the graphicsacceleration module 446. Data from the WD 484 may be stored in registers445 and used by the MMU 439, interrupt management circuit 447 and/orcontext management circuit 446 as illustrated. For example, oneembodiment of the MMU 439 includes segment/page walk circuitry foraccessing segment/page tables 486 within the OS virtual address space485. The interrupt management circuit 447 may process interrupt events492 received from the graphics acceleration module 446. When performinggraphics operations, an effective address 493 generated by a graphicsprocessing engine 431-432, N is translated to a real address by the MMU439.

In one embodiment, the same set of registers 445 are duplicated for eachgraphics processing engine 431-432, N and/or graphics accelerationmodule 446 and may be initialized by the hypervisor or operating system.Each of these duplicated registers may be included in an acceleratorintegration slice 490. Exemplary registers that may be initialized bythe hypervisor are shown in Table 1.

TABLE 1 Hypervisor Initialized Registers 1 Slice Control Register 2 RealAddress (RA) Scheduled Processes Area Pointer 3 Authority Mask OverrideRegister 4 Interrupt Vector Table Entry Offset 5 Interrupt Vector TableEntry Limit 6 State Register 7 Logical Partition ID 8 Real address (RA)Hypervisor Accelerator Utilization Record Pointer 9 Storage DescriptionRegister

Exemplary registers that may be initialized by the operating system areshown in Table 2.

TABLE 2 Operating System Initialized Registers 1 Process and ThreadIdentification 2 Effective Address (EA) Context Save/Restore Pointer 3Virtual Address (VA) Accelerator Utilization Record Pointer 4 VirtualAddress (VA) Storage Segment Table Pointer 5 Authority Mask 6 Workdescriptor

In one embodiment, each WD 484 is specific to a particular graphicsacceleration module 446 and/or graphics processing engine 431-432, N. Itcontains all the information a graphics processing engine 431-432, Nrequires to do its work or it can be a pointer to a memory locationwhere the application has set up a command queue of work to becompleted.

FIG. 4E illustrates additional details for one embodiment of a sharedmodel. This embodiment includes a hypervisor real address space 498 inwhich a process element list 499 is stored. The hypervisor real addressspace 498 is accessible via a hypervisor 496 which virtualizes thegraphics acceleration module engines for the operating system 495.

The shared programming models allow for all or a subset of processesfrom all or a subset of partitions in the system to use a graphicsacceleration module 446. There are two programming models where thegraphics acceleration module 446 is shared by multiple processes andpartitions: time-sliced shared and graphics directed shared.

In this model, the system hypervisor 496 owns the graphics accelerationmodule 446 and makes its function available to all operating systems495. For a graphics acceleration module 446 to support virtualization bythe system hypervisor 496, the graphics acceleration module 446 mayadhere to the following requirements: 1) An application's job requestmust be autonomous (that is, the state does not need to be maintainedbetween jobs), or the graphics acceleration module 446 must provide acontext save and restore mechanism. 2) An application's job request isguaranteed by the graphics acceleration module 446 to complete in aspecified amount of time, including any translation faults, or thegraphics acceleration module 446 provides the ability to preempt theprocessing of the job. 3) The graphics acceleration module 446 must beguaranteed fairness between processes when operating in the directedshared programming model.

In one embodiment, for the shared model, the application 480 is requiredto make an operating system 495 system call with a graphics accelerationmodule 446 type, a work descriptor (WD), an authority mask register(AMR) value, and a context save/restore area pointer (CSRP). Thegraphics acceleration module 446 type describes the targetedacceleration function for the system call. The graphics accelerationmodule 446 type may be a system-specific value. The WD is formattedspecifically for the graphics acceleration module 446 and can be in theform of a graphics acceleration module 446 command, an effective addresspointer to a user-defined structure, an effective address pointer to aqueue of commands, or any other data structure to describe the work tobe done by the graphics acceleration module 446. In one embodiment, theAMR value is the AMR state to use for the current process. The valuepassed to the operating system is similar to an application setting theAMR. If the accelerator integration circuit 436 and graphicsacceleration module 446 implementations do not support a User AuthorityMask Override Register (UAMOR), the operating system may apply thecurrent UAMOR value to the AMR value before passing the AMR in thehypervisor call. The hypervisor 496 may optionally apply the currentAuthority Mask Override Register (AMOR) value before placing the AMRinto the process element 483. In one embodiment, the CSRP is one of theregisters 445 containing the effective address of an area in theapplication's address space 482 for the graphics acceleration module 446to save and restore the context state. This pointer is optional if nostate is required to be saved between jobs or when a job is preempted.The context save/restore area may be pinned system memory.

Upon receiving the system call, the operating system 495 may verify thatthe application 480 has registered and been given the authority to usethe graphics acceleration module 446. The operating system 495 thencalls the hypervisor 496 with the information shown in Table 3.

TABLE 3 OS to Hypervisor Call Parameters 1 A work descriptor (WD) 2 AnAuthority Mask Register (AMR) value (potentially masked). 3 An effectiveaddress (EA) Context Save/Restore Area Pointer (CSRP) 4 A process ID(PID) and optional thread ID (TID) 5 A virtual address (VA) acceleratorutilization record pointer (AURP) 6 The virtual address of the storagesegment table pointer (SSTP) 7 A logical interrupt service number (LISN)

Upon receiving the hypervisor call, the hypervisor 496 verifies that theoperating system 495 has registered and been given the authority to usethe graphics acceleration module 446. The hypervisor 496 then puts theprocess element 483 into the process element linked list for thecorresponding graphics acceleration module 446 type. The process elementmay include the information shown in Table 4.

TABLE 4 Process Element Information 1 A work descriptor (WD) 2 AnAuthority Mask Register (AMR) value (potentially masked). 3 An effectiveaddress (EA) Context Save/Restore Area Pointer (CSRP) 4 A process ID(PID) and optional thread ID (TID) 5 A virtual address (VA) acceleratorutilization record pointer (AURP) 6 The virtual address of the storagesegment table pointer (SSTP) 7 A logical interrupt service number (LISN)8 Interrupt vector table, derived from the hypervisor call parameters. 9A state register (SR) value 10 A logical partition ID (LPID) 11 A realaddress (RA) hypervisor accelerator utilization record pointer 12 TheStorage Descriptor Register (SDR)

In one embodiment, the hypervisor initializes a plurality of acceleratorintegration slice 490 registers 445.

As illustrated in FIG. 4F, one embodiment of the invention employs aunified memory addressable via a common virtual memory address spaceused to access the physical processor memories 401-402 and GPU memories420-423. In this implementation, operations executed on the GPUs 410-413utilize the same virtual/effective memory address space to access theprocessors memories 401-402 and vice versa, thereby simplifyingprogrammability. In one embodiment, a first portion of thevirtual/effective address space is allocated to the processor memory401, a second portion to the second processor memory 402, a thirdportion to the GPU memory 420, and so on. The entire virtual/effectivememory space (sometimes referred to as the effective address space) isthereby distributed across each of the processor memories 401-402 andGPU memories 420-423, allowing any processor or GPU to access anyphysical memory with a virtual address mapped to that memory.

In one embodiment, bias/coherence management circuitry 494A-494E withinone or more of the MMUs 439A-439E ensures cache coherence between thecaches of the host processors (e.g., 405) and the GPUs 410-413 andimplements biasing techniques indicating the physical memories in whichcertain types of data should be stored. While multiple instances ofbias/coherence management circuitry 494A-494E are illustrated in FIG.4F, the bias/coherence circuitry may be implemented within the MMU ofone or more host processors 405 and/or within the acceleratorintegration circuit 436.

One embodiment allows GPU-attached memory 420-423 to be mapped as partof system memory, and accessed using shared virtual memory (SVM)technology, but without suffering the typical performance drawbacksassociated with full system cache coherence. The ability to GPU-attachedmemory 420-423 to be accessed as system memory without onerous cachecoherence overhead provides a beneficial operating environment for GPUoffload. This arrangement allows the host processor 405 software tosetup operands and access computation results, without the overhead oftradition I/O DMA data copies. Such traditional copies involve drivercalls, interrupts and memory mapped I/O (MMIO) accesses that are allinefficient relative to simple memory accesses. At the same time, theability to access GPU attached memory 420-423 without cache coherenceoverheads can be critical to the execution time of an offloadedcomputation. In cases with substantial streaming write memory traffic,for example, cache coherence overhead can significantly reduce theeffective write bandwidth seen by a GPU 410-413. The efficiency ofoperand setup, the efficiency of results access, and the efficiency ofGPU computation all play a role in determining the effectiveness of GPUoffload.

In one implementation, the selection of between GPU bias and hostprocessor bias is driven by a bias tracker data structure. A bias tablemay be used, for example, which may be a page-granular structure (i.e.,controlled at the granularity of a memory page) that includes 1 or 2bits per GPU-attached memory page. The bias table may be implemented ina stolen memory range of one or more GPU-attached memories 420-423, withor without a bias cache in the GPU 410-413 (e.g., to cachefrequently/recently used entries of the bias table). Alternatively, theentire bias table may be maintained within the GPU.

In one implementation, the bias table entry associated with each accessto the GPU-attached memory 420-423 is accessed prior the actual accessto the GPU memory, causing the following operations. First, localrequests from the GPU 410-413 that find their page in GPU bias areforwarded directly to a corresponding GPU memory 420-423. Local requestsfrom the GPU that find their page in host bias are forwarded to theprocessor 405 (e.g., over a high-speed link as discussed above). In oneembodiment, requests from the processor 405 that find the requested pagein host processor bias complete the request like a normal memory read.Alternatively, requests directed to a GPU-biased page may be forwardedto the GPU 410-413. The GPU may then transition the page to a hostprocessor bias if it is not currently using the page.

The bias state of a page can be changed either by a software-basedmechanism, a hardware-assisted software-based mechanism, or, for alimited set of cases, a purely hardware-based mechanism.

One mechanism for changing the bias state employs an API call (e.g.OpenCL), which, in turn, calls the GPU's device driver which, in turn,sends a message (or enqueues a command descriptor) to the GPU directingit to change the bias state and, for some transitions, perform a cacheflushing operation in the host. The cache flushing operation is requiredfor a transition from host processor 405 bias to GPU bias, but is notrequired for the opposite transition.

In one embodiment, cache coherency is maintained by temporarilyrendering GPU-biased pages uncacheable by the host processor 405. Toaccess these pages, the processor 405 may request access from the GPU410 which may or may not grant access right away, depending on theimplementation. Thus, to reduce communication between the processor 405and GPU 410 it is beneficial to ensure that GPU-biased pages are thosewhich are required by the GPU but not the host processor 405 and viceversa.

Graphics Processing Pipeline

FIG. 5 illustrates a graphics processing pipeline 500, according to anembodiment. In one embodiment a graphics processor can implement theillustrated graphics processing pipeline 500. The graphics processor canbe included within the parallel processing subsystems as describedherein, such as the parallel processor 200 of FIG. 2, which, in oneembodiment, is a variant of the parallel processor(s) 112 of FIG. 1. Thevarious parallel processing systems can implement the graphicsprocessing pipeline 500 via one or more instances of the parallelprocessing unit (e.g., parallel processing unit 202 of FIG. 2) asdescribed herein. For example, a shader unit (e.g., graphicsmultiprocessor 234 of FIG. 3) may be configured to perform the functionsof one or more of a vertex processing unit 504, a tessellation controlprocessing unit 508, a tessellation evaluation processing unit 512, ageometry processing unit 516, and a fragment/pixel processing unit 524.The functions of data assembler 502, primitive assemblers 506, 514, 518,tessellation unit 510, rasterizer 522, and raster operations unit 526may also be performed by other processing engines within a processingcluster (e.g., processing cluster 214 of FIG. 3) and a correspondingpartition unit (e.g., partition unit 220A-220N of FIG. 2). The graphicsprocessing pipeline 500 may also be implemented using dedicatedprocessing units for one or more functions. In one embodiment, one ormore portions of the graphics processing pipeline 500 can be performedby parallel processing logic within a general purpose processor (e.g.,CPU). In one embodiment, one or more portions of the graphics processingpipeline 500 can access on-chip memory (e.g., parallel processor memory222 as in FIG. 2) via a memory interface 528, which may be an instanceof the memory interface 218 of FIG. 2.

In one embodiment the data assembler 502 is a processing unit thatcollects vertex data for surfaces and primitives. The data assembler 502then outputs the vertex data, including the vertex attributes, to thevertex processing unit 504. The vertex processing unit 504 is aprogrammable execution unit that executes vertex shader programs,lighting and transforming vertex data as specified by the vertex shaderprograms. The vertex processing unit 504 reads data that is stored incache, local or system memory for use in processing the vertex data andmay be programmed to transform the vertex data from an object-basedcoordinate representation to a world space coordinate space or anormalized device coordinate space.

A first instance of a primitive assembler 506 receives vertex attributesfrom the vertex processing unit 504. The primitive assembler 506readings stored vertex attributes as needed and constructs graphicsprimitives for processing by tessellation control processing unit 508.The graphics primitives include triangles, line segments, points,patches, and so forth, as supported by various graphics processingapplication programming interfaces (APIs).

The tessellation control processing unit 508 treats the input verticesas control points for a geometric patch. The control points aretransformed from an input representation from the patch (e.g., thepatch's bases) to a representation that is suitable for use in surfaceevaluation by the tessellation evaluation processing unit 512. Thetessellation control processing unit 508 can also compute tessellationfactors for edges of geometric patches. A tessellation factor applies toa single edge and quantifies a view-dependent level of detail associatedwith the edge. A tessellation unit 510 is configured to receive thetessellation factors for edges of a patch and to tessellate the patchinto multiple geometric primitives such as line, triangle, orquadrilateral primitives, which are transmitted to a tessellationevaluation processing unit 512. The tessellation evaluation processingunit 512 operates on parameterized coordinates of the subdivided patchto generate a surface representation and vertex attributes for eachvertex associated with the geometric primitives.

A second instance of a primitive assembler 514 receives vertexattributes from the tessellation evaluation processing unit 512, readingstored vertex attributes as needed, and constructs graphics primitivesfor processing by the geometry processing unit 516. The geometryprocessing unit 516 is a programmable execution unit that executesgeometry shader programs to transform graphics primitives received fromprimitive assembler 514 as specified by the geometry shader programs. Inone embodiment the geometry processing unit 516 is programmed tosubdivide the graphics primitives into one or more new graphicsprimitives and calculate parameters used to rasterize the new graphicsprimitives.

In some embodiments the geometry processing unit 516 can add or deleteelements in the geometry stream. The geometry processing unit 516outputs the parameters and vertices specifying new graphics primitivesto primitive assembler 518. The primitive assembler 518 receives theparameters and vertices from the geometry processing unit 516 andconstructs graphics primitives for processing by a viewport scale, cull,and clip unit 520. The geometry processing unit 516 reads data that isstored in parallel processor memory or system memory for use inprocessing the geometry data. The viewport scale, cull, and clip unit520 performs clipping, culling, and viewport scaling and outputsprocessed graphics primitives to a rasterizer 522.

The rasterizer 522 can perform depth culling and other depth-basedoptimizations. The rasterizer 522 also performs scan conversion on thenew graphics primitives to generate fragments and output those fragmentsand associated coverage data to the fragment/pixel processing unit 524.The fragment/pixel processing unit 524 is a programmable execution unitthat is configured to execute fragment shader programs or pixel shaderprograms. The fragment/pixel processing unit 524 transforming fragmentsor pixels received from rasterizer 522, as specified by the fragment orpixel shader programs. For example, the fragment/pixel processing unit524 may be programmed to perform operations included but not limited totexture mapping, shading, blending, texture correction and perspectivecorrection to produce shaded fragments or pixels that are output to araster operations unit 526. The fragment/pixel processing unit 524 canread data that is stored in either the parallel processor memory or thesystem memory for use when processing the fragment data. Fragment orpixel shader programs may be configured to shade at sample, pixel, tile,or other granularities depending on the sampling rate configured for theprocessing units.

The raster operations unit 526 is a processing unit that performs rasteroperations including, but not limited to stencil, z test, blending, andthe like, and outputs pixel data as processed graphics data to be storedin graphics memory (e.g., parallel processor memory 222 as in FIG. 2,and/or system memory 104 as in FIG. 1, to be displayed on the one ormore display device(s) 110 or for further processing by one of the oneor more processor(s) 102 or parallel processor(s) 112. In someembodiments the raster operations unit 526 is configured to compress zor color data that is written to memory and decompress z or color datathat is read from memory.

Asynchronous Display

FIG. 6A is a block diagram 600 illustrating a conventional raster scanprocess for displaying an image on a display. Block diagram 600 includesa computing device 602 communicatively coupled to a 4×4 raster scandisplay 604. Note that the 4×4 raster scan display 604 is used forillustrative purposes only. One skilled in the art would recognize thatthe small number of pixels in the display 604 is greatly minimalized. Ina real world display, such as, for example, an HD (High Definition)display, there may be 1920×1080 pixels. Computing device 602 mayinclude, inter alia, a central processing unit (CPU), a graphicsprocessing unit (GPU), and memory, such as, but not limited to, randomaccess memory. Computing device 602 may be any device that outputs animage, picture, video, or other visual data to be displayed. Forexample, computing device 602 may be, but is not limited to, a camera, aDVD player, a gaming system, a graphics adaptor, a mobile phone, atablet, a wearable device, etc. Computing device 602 outputs an image tobe displayed on display 604. In one embodiment, display 604 may be abuilt-in component of computing device 602, such as, but not limited to,a tablet, a phone, or a wearable device. In another embodiment, display604 may be externally connected to computing device 602.

The process of displaying an image on the display 604 is referred to asraster scanning. Raster scanning updates every pixel on the display 604on a per frame basis, one pixel at a time. It updates each row of pixelsfrom left to right and updates each row from top to bottom. The order inwhich pixels are updated on display 604 is illustrated using the linesand arrows depicted in FIG. 6A.

As previously indicated, a frame rate of 30 frames per second is goodfor human perception, but when virtual reality, augmented reality, orgaming is added, 30 frames per second is not enough to control latency.Systems today try to solve the latency problem by increasing the framesper second to 90 or 120 frames per second. This helps to keep thelatency down, but requires more compute power. Embodiments are presentedbelow that help to reduce latency while optimizing power.

In one embodiment, the data to be displayed is sent asynchronously.Instead of having to refresh every pixel at a certain rate, only thepixels that are changing from one frame to the next are sent. Forexample, if you are watching a scene in which the background stays thesame and the only thing changing from frame to frame is the expressionon a character's face, then only the pixels on the displayrepresentative of the facial expression that is changing are refreshed.The background pixels remain the same and, therefore, do not need to berefreshed.

FIG. 6B is a block diagram 610 illustrating computing device 602 onlyupdating pixels on display 604 that have changed. As shown in FIG. 6B,instead of having a circular shape (as shown in FIG. 6A), pixel 606 nowrepresents the shape of an octagon. Computing device 602, whenrefreshing the display 604, only sent one pixel, that is, pixel 606 (thepixel that changed). The remaining pixels did not change, and therefore,were not updated or refreshed. Since pixel 606 was updatedasynchronously when it changed from a circle to an octagon rather thanon the next frame update, the latency for this update is reduced. A lotless power is consumed to update one pixel, pixel 606, versus updatingall sixteen pixels on display 604.

Block Based Camera Updates

In one embodiment, a camera provides a mechanism to capture an image onthe camera and determine, from one image to the next image, the pixelbased block(s) that has been updated. The camera, after determining theupdated block or region, sends the updated block/region, along withmetadata including the corresponding pixel block address (x,y)coordinates, to an SOC (System on a Chip) or memory panel display tocomposite the updated block/region with the previous frame for displayon the memory panel display.

FIG. 7A is an exemplary block diagram 700 for block based camera updatesaccording to an embodiment. Block diagram 700 includes a camera 702, asystem-on-a-chip 706, memory 708, and a display 710. The camera 702connects to the system-on-a-chip 706 and the system-on-a-chip 706connects to memory 708 and to the display 710. The SOC includes, interalia, one or more memories, an ISP (image signal processor) forprocessing images, a CPU, and a GPU. As shown in FIG. 7A, the camera 702determines an updated block/region 704. The updated block/region 704represents the change between a previous image n−1 and a current imagen.

FIG. 7E illustrates an updated block/region according to an embodiment.Frame 0 represents image n−1 and frame 1 represents image n. Frame 1 isidentical to Frame 0 except for a small block/region of Frame 1, whichis indicated as the updated block/region 704. Instead of processing theentire Frame 1, only the updated block/region 704 is processed from thecamera 702 to the display 710. The updated block/region 704 isdetermined by the camera 702.

Returning to FIG. 7A, the updated block 704 is passed to the SOC 706along with metadata including pixel block address coordinates (X, Y)that define the location for the updated block 704 in the image. In oneembodiment, the SOC 706 merges the updated block 704 with the previousimage n−1, which is stored in memory 708. The SOC 706 uses the pixelblock address coordinates (X, Y) to merge the updated block 704 at theappropriate location on the previous image n−1. The SOC 706 then storesthe image with the updated block 704 in memory 708 and sends the imagethat includes the updated block 704 to the display 710. The display 710is updated with the image that includes the updated block 704 (as shownin the display 710).

FIG. 7B is an exemplary flow diagram describing a method for a camera todetermine an updated block according to an embodiment. The processbegins in block 718 where the process proceeds to block 720.

Immediately after the process begins, in block 720, the camera sets afirst image bit to 1. The first image bit, when set, indicates that thecamera is about to take a first image. The process proceeds to block722.

In block 722, the camera takes an image, referred to as image n. Image nis stored in the camera memory. The process then proceeds to decisionblock 723.

In decision block 723, it is determined if the first image bit is set.If it is determined that the first image bit is set, image n is to besent to the SOC. The process then proceeds to block 725.

In block 725, image n is sent to the SOC along with the first image bitto indicate that image n is the first image and should be displayed. Theprocess proceeds to decision block 727.

Returning to decision block 723, if it is determined that the firstimage bit is 0, then the process proceeds to block 724.

In block 724, the camera determines what regions changed from theprevious image n−1. In one embodiment, the camera, in determining thewhat regions changed (i.e., the updated block(s) 704) divides an imageinto a plurality of small regions. For each region, a CRC (cyclicredundancy check) value is determined. The CRC value is used todetermine if a region has changed from one image to the next. A moredetailed description of the process used to determine what regions havechanged from the previous image n−1 is provided below with reference toFIG. 7D. In another embodiment, the camera may use a different algorithmto determine what regions changed from image n−1 to image n, such as,for example, a histogram algorithm. Histograms and other algorithms arewell known in the art. The process then proceeds to block 726.

In block 726, each updated region along with metadata including thecorresponding X, Y coordinates indicating the position of the region inimage n that changed from the previous image n−1 is sent to the SOC 706.The process then proceeds to decision block 727.

In decision block 727, the SOC 706 will check to see if this is a firstimage. If this is a first image, i.e., the first image bit is set to 1,the first image is to be displayed, and the process proceeds to block729. If the image is not a first image, the SOC will merge the updatedregion(s) with the previous image n−1 to create the new image to bedisplayed (block 728). The new image, referred to as image n, is storedin memory 708. The process then proceeds to block 729.

In block 729, the format of image n is modified to match the displayformat. The process then proceeds to block 731.

In block 731, the formatted image is sent to the display. The processthen proceeds to block 734.

In block 734, the formatted image is displayed on display 710. The firstimage bit is set to zero (0). This is an indication that the nextcaptured image will not be the first image. The process then proceedsback to block 722 to capture the next image.

In one embodiment, display 710 may include memory panels. The memorypanels allow for the merging of updated regions to take place on display710 instead of the SOC. FIG. 7C is a flow diagram illustrating anexemplary method for block based camera updates using a display withmemory panels according to an embodiment. The process begins in block718 where the process proceeds to block 720.

Immediately after the process begins, in block 720, the camera sets afirst image bit to 1. This first image bit, when set, indicates that thecamera is about to take a first image. The process then proceeds toblock 722.

In block 722, the camera takes an image, referred to as image n. Image nis stored in the camera memory. The process then proceeds to decisionblock 723.

In decision block 723, it is determined if the first image bit is set.If it is determined that the first image bit is set, image n is to besent to the SOC. The process then proceeds to block 725.

In block 725, image n is sent to the SOC along with the first image bitto indicate that image n is the first image and should be displayed. Theprocess proceeds to block 727.

Returning to decision block 723, if it is determined that the firstimage bit is 0, then the process proceeds to block 724.

In block 724, the camera determines what regions changed from theprevious image n−1. A more detailed description of the process used todetermine what regions have changed from the previous image n−1 isprovided below with reference to FIG. 7D. The process then proceeds toblock 726.

In block 726, each updated region along with metadata including thecorresponding X, Y coordinates indicating the position of the region inimage n is sent to the SOC 706. The image first bit is also sent to theSOC. The process then proceeds to decision block 727.

In decision block 727, it is determined if the first image bit is set.If the first image bit is set, the process proceeds to block 729.

In block 729, the image format for image n is modified to match thedisplay format. The process then proceeds to block 731.

In block 731, the formatted image is sent to the display. The processthen proceeds to block 734.

Returning to decision block 727, if the first image bit is 0, the imageformat for each updated region is modified to match the display formatin block 730. The process then proceeds to block 732.

In block 732, the formatted updated regions and their corresponding Xand Y values are sent to the display. The process then proceeds to block733.

As previously indicated, the display 710 includes memory panels. Thememory panels allow for the display to store the previous image n−1. Inblock 733, the display retrieves the previous image n−1 from the displaymemory panel and merges the updated regions with the previous image n−1to create a new image n. The new image n is stored in the display memorypanel. The process proceeds to block 734.

In block 734, the image n is displayed on the display 710. The firstimage bit is set to zero (0). This is an indication that the nextcaptured image will not be the first image. The process then proceedsback to block 722 to capture the next image.

FIG. 7D is a flow diagram illustrating an exemplary method fordetermining update regions for block based camera updates according toan embodiment. The process begins in block 740 where the processproceeds to block 742.

In block 742, the image is divided into small regions. The process thenproceeds to block 744.

In block 744 a CRC value for each region is determined and the CRCvalues are stored in the camera memory. The process then proceeds toblocks 746 through 752.

In blocks 746 through 752, the following process occurs for each region:(1) compare the CRC value for the current image, image n, with the CRCvalue for the previous image, image n−1 (block 748); (2) if the CRCvalues are different (decision block 750), then select the region as anupdated region and tag the corresponding X,Y coordinates for the updatedregion (block 752); and (3) return to block 748 until all regions havebeen compared.

The process then proceeds to block 754. In block 754 the process ends.

Asynchronous Gaming System

An asynchronous, event driven exemplary gaming system 800 is shown inFIG. 8. Gaming system 800 is a specialized computer system forinteractive video game play and display. Gaming system 800 includes,inter alia, a CPU, a GPU, random-access memory (RAM), speakers, etc.Gaming system 800 processes video games and renders interactive videofrom the game via an asynchronous display 814. As shown in FIG. 8,gaming system 800 includes input devices, such as, but not limited to,an eye tracker 802, a differential video camera 804, a 6DOF (6° offreedom) tracker 806, a gesture tracker 808, and a game controller 810.Gaming system 800 may also receive input data/actions from remoteplayers over the Internet 812. Gaming system 800 outputs audio signalsvia speakers (not explicitly shown) and sends updated video content(address and colored pixel content) to the asynchronous display 814 forupdating the display with content that has changed based on one or moreevents that have occurred during play of a game.

Eye tracker 802 monitors the changing position of the eyes of a player.It tracks how the eyes move relative to the player's head. Eye tracker802 outputs the change in eye position and the time in which the changeoccurred.

Differential video camera 804 tracks the amount of light falling on eachpixel and when that light goes up or down it sends an event indicatingthat the brightness has gone up or down. Differential video camera 804outputs the change in brightness for a pixel and the correspondingaddress of that pixel.

6DOF tracker 806 tracks a player's head position in 6° of freedom, i.e.,roll, pitch, yaw, x, y, and z. 6DOF tracker 806 outputs the direction inwhich the head position moved and the time at which the head positionchanged.

Gesture tracker 808 tracks a player's hand movements to detect if theplayer made a certain symbol with their hands or if they made a certainmotion with their hands that has some relevance to the game beingplayed. In other words, gesture tracker 808 detects if the player made acertain gesture with their hands. Gesture tracker 808 outputs thegesture that was made and the location, relative to the image on display814, in which the gesture was made.

Game controller 810 is a device used with gaming system 800 to provideinput to a video game being played. Game controller 810 may includebuttons and knobs. The buttons and knobs are typically used to controlan object or a character in a video game. Game controller 810 outputs asignal representative of the buttons and knobs used by a player of thegame.

Gaming system 800 may also receive actions as input from one or moreremote players of the game over the Internet 812. The actions may rangefrom controller buttons and knobs to gestures, head movements, eyemovements, pixel changes along with the corresponding address, etc.

In one embodiment, an asynchronous, event driven system uses eventdriven cameras and sensors to drive an asynchronous gaming system 800,which in turn, drives an asynchronous display 814. In an embodiment,instead of updating every pixel on display 814 at a fixed frame rate,the interface to the display 814 is modified to only send changes to thedisplay when an event occurs. For example, an event may be, but is notlimited to, a change in head and/or eye position, a new gesture, acontroller change, a camera change, a change in action from a remoteplayer over the Internet, etc. At the time in which anyone of theseevents occurs, the gaming system 800 will send the address and pixelchange to the display. The display will then update the location of thechange using the pixel address with the pixels representing the change.

Frame/Update Scheduler Based on Prioritized Inputs

The local sensors 802, 804, 806, and 808, the game controller 810, andactions from remote players over the Internet are all asynchronousinputs into the gaming system 800. With so many asynchronous inputs intothe gaming system 800, a method of listening to the asynchronous inputsand determining when enough things have changed to cause a scene changethat requires rendering a new frame or block update is needed. In anembodiment, a scheduler may be used with an asynchronous display todetermine when to listen to the asynchronous inputs and determine whenenough things have changed to render a new frame or block update. Thescheduler uses event inputs with the addition of relative weighting toeach event input to determine when to render the new frame or block.

FIG. 9 shows an example scoring table based on the event inputs to thegaming system 800. The values in the scoring table may be applicationspecific and therefore, may be different for different gaming scenarios.For example, the events driving the display may depend upon the type ofgame being played. If the game being played requires the heavy use of aheadset, events based on the headset may be more heavily weighted thanother inputs.

As shown in the example of FIG. 9, example events that may occur tocause the scheduler to determine that a frame or a block should berendered and displayed on the asynchronous display include a smooth eyetracking event, a saccadic eye tracking event, a controller event, ahead position change event, a camera event, a network event, and agesture event. Each event has an initial score to be applied at timet=0. For example, smooth eye tracking at time t=0 is a score of 50points while a network event at t=0 is a score of 5 points. According tothe table, the scores are updated every millisecond. For example, smootheye tracking is increased every millisecond by 20 points and a networkevent is increased every millisecond by 10 points. The table alsoincludes an update limit for each event. For example, smooth eyetracking has an update limit of 10 msec. while a network event has anupdate limit of 300 msec.

FIG. 10 is a flow diagram 1000 illustrating an exemplary event drivenprocess for event driven frame or block updates on an asynchronousdisplay according to an embodiment. The process begins with block 1002,where the process immediately proceeds to 1004.

In block 1004, the scheduler waits for an event input or a timeout. Theprocess then proceeds to block 1006.

In block 1006, the corresponding weight associated with the event thatis occurring is added to the score. The process then proceeds todecision block 1008.

In decision block 1008, it is determined whether the limit has beenexceeded. If the limit has not been exceeded, the process returns toblock 1004 where it waits for an event input or a timeout.

Returning to decision block 1008, if the limit has been exceeded, theprocess proceeds to block 1010. In block 1010, a frame or a block isupdated based on the event. The process then proceeds to block 1012.

In block 1012, the score is cleared. The process then proceeds back toblock 1004 where it waits for an event input or a timeout.

Using a simple situation in which only a smooth eye tracking eventoccurs, the limit is set to 200 points and, at block 1004, the eventinput of smooth eye tracking is received. In block 1006, the score isupdated to 50 points, the score for the smooth eye tracking at t0. Atdecision block 1008, it is determined that the limit has not beenexceeded (t0) (the current score of 50 points does not exceed the limitof 200 points), so the process proceeds back to block 1004. At block1004, no new events have occurred, but at t=1 msec. a timeout occurs,and the process proceeds to block 1006 where the score gets increased by20 points. So at time t1=1 msec, the score is now 70. If no new eventsoccur, this process will repeat itself every msec. until the scoreexceeds the limit. In other words, at t=8 msec. the score will be 210points which is over the 200 point limit used in this example. Theprocess then proceeds to block 1010 where the frame or block is renderedand displayed. The score is then cleared at block 1012, and the processproceeds back to block 1004, where it waits for another event input.

Display Technology

Turning now to FIG. 11, a performance-enhanced computing system 1100 isshown. In the illustrated example, a processor 1110 is coupled to adisplay 1120. The processor 1110 may generally generate images to bedisplayed on an LCD panel 1150 of the display 1120. In one example, theprocessor 1110 includes a communication interface such as, for example,a video graphics array (VGA), a DisplayPort (DP) interface, an embeddedDisplayPort (eDP) interface, a high-definition multimedia interface(HDMI), a digital visual interface (DVI), and so forth. The processor1110 may be a graphics processor (e.g., graphics processing unit/GPU)that processes graphics data and generates the images (e.g., videoframes, still images) displayed on the LCD panel 1150. Moreover, theprocessor 1110 may include one or more image processing pipelines thatgenerate pixel data. The image processing pipelines may comply with theOPENGL architecture, or other suitable architecture. Additionally, theprocessor 1110 may be connected to a host processor (e.g., centralprocessing unit/CPU), wherein the host processor executes one or moredevice drivers that control and/or interact with the processor 1110.

The illustrated display 1120 includes a timing controller (TCON) 1130,which may individually address different pixels in the LCD panel 1150and update each individual pixel in the LCD panel 1150 per refreshcycle. In this regard, the LCD panel 1150 may include a plurality ofliquid crystal elements such as, for example, a liquid crystal andintegrated color filter. Each pixel of the LCD panel 1150 may include atrio of liquid crystal elements with red, green, and blue color filters,respectively. The LCD panel 1150 may arrange the pixels in atwo-dimensional (2D) array that is controlled via row drivers 1152 andcolumn drivers 1154 to update the image being displayed by the LCD panel1150. Thus, the TCON 1130 may drive the row drivers 1152 and the columndrivers 1154 to address specific pixels of the LCD panel 1150. The TCON1130 may also adjust the voltage provided to the liquid crystal elementsin the pixel to change the intensity of the light passing through eachof the three liquid crystal elements and, therefore, change the color ofthe pixel displayed on the surface of the LCD panel 1150.

A backlight 1160 may include a plurality of light emitting elements suchas, for example, light emitting diodes (LEDs), that are arranged at anedge of the LCD panel 1150. Accordingly, the light generated by the LEDsmay be dispersed through the LCD panel 1150 by a diffuser (not shown).In another example, the LEDs are arranged in a 2D array directly behindthe LCD panel 1150 in a configuration sometimes referred to as directbacklighting because each LED disperses light through one or morecorresponding pixels of the LCD panel 1150 positioned in front of theLED. The light emitting elements may also include compact fluorescentlamps (CFL's) arranged along one or more edges of the LCD panel 1150. Toeliminate multiple edges, the combination of edges may be altered toachieve selective illumination of a region, wherein less than the totalset of lighting elements is used with less power.

The light emitting elements may also include one or more sheets ofelectroluminescent material placed behind the LCD panel 1150. In such acase, light from the surface of the sheet may be dispersed through thepixels of the LCD panel 1150. Additionally, the sheet may be dividedinto a plurality of regions such as, for example, quadrants. In oneexample, each region is individually controlled to illuminate only aportion of the LCD panel 1150. Other backlighting solutions may also beused.

The illustrated display 1120 also includes a backlight controller (BLC)1140 that provides a voltage to the light emitting elements of thebacklight 1160. For example, the BLC 1140 may include a pulse widthmodulation (PWM) driver (not shown) to generate a PWM signal thatactivates at least a portion of the light emitting elements of thebacklight 1160. The duty cycle and frequency of the PWM signal may causethe light generated by the light emitting elements to dim. For example,a 100% duty cycle may correspond to the light emitting elements beingfully on and a 0% duty cycle may correspond to the light emittingelements being fully off. Thus, intermediate duty cycles (e.g., 25%,50%) typically cause the light emitting elements to be turned on for aportion of a cycle period that is proportional to the percentage of theduty cycle. The cycle period of may be fast enough that the blinking ofthe light emitting elements is not noticeable to the human eye.Moreover, the effect to the user may be that the level of the lightemitted by the backlight 1160 is lower than if the backlight 1160 werefully activated. The BLC 1140 may be separate from or incorporated intothe TCON 1130.

Alternatively, an emissive display system may be used where the LCDpanel 1150 would be replaced by an emissive display panel (e.g. organiclight emitting diode/OLED) the backlight 1160 would be omitted, and therow and column drivers 1152 and 1154, respectively, may be used todirectly modulate pixel color and brightness.

Distance Based Display Resolution

FIG. 12A shows a scenario in which a user 1218 interacts with a dataprocessing device 1200 containing a display unit 1228. The displayprocessing device 1200 may include, for example, a notebook computer, adesktop computer, a tablet computer, a convertible tablet, a mobileInternet device (MID), a personal digital assistant (PDA), a wearabledevice (e.g., head mounted display/HMD), a media player, etc., or anycombination thereof. The illustrated data processing device 1200includes a processor 1224 (e.g., embedded controller, microcontroller,host processor, graphics processor) coupled to a memory 1222, which mayinclude storage locations that are addressable through the processor1224. As will be discussed in greater detail, a distance sensor 1210 mayenable distance based display resolution with respect to the displayunits 1228.

The illustrated memory 1222 includes display data 1226 that is to berendered on the display unit 1228. In one example, the processor 1224conducts data conversion on the display data 1226 prior to presentingthe display data 1226 on the display unit 1228. A post-processing engine1214 may execute on the processor 1224 to receive the display data 1226and an output of the distance sensor 1210. The post-processing engine1214 may modify the display data 1226 to enhance the readability ofscreen content on the display unit 1228, reduce power consumption in thedata processing device 1200, etc., or any combination thereof.

The illustrated memory 1222 stores a display resolution setting 1216, inaddition to an operating system 1212 and an application 1220. Thedisplay resolution setting 1216 may specify a number of pixels of thedisplay data 1226 to be presented on the display unit 1228 along alength dimension and a width dimension. If the display data 1226 asgenerated by the application 1220 is incompatible with the format of thedisplay unit 1228, the processor 1224 may configure the scale of thedisplay data 1226 to match the format of the display units 1228. In thisregard, the display resolution setting 1216 may be associated withand/or incorporated into configuration data that defines other settingsfor the display unit 1228. Moreover, the display resolution setting 1216may be defined in terms of unit distance or area (e.g., pixels perinch/PPI), or other suitable parameter.

The application 1220 may generate a user interface, wherein the user1218 may interact with the user interface to select the displayresolution setting 1216 from one or more options provided through theuser interface, enter the display resolution setting 1216 as a requestedvalue, and so forth. Thus, the display data 1226 may be resized to fitinto the display resolution setting 1216 prior to being rendered on thedisplay unit 1228.

The distance sensor 1210 may track the distance between the user 1218and the display unit 1228, wherein distance sensing may be triggeredthrough a physical button associated with the data processing device1200/display unit 1228, through the user interface provided by theapplication 1220 and/or loading of the operating system 1220, and soforth. For example, during a boot of the data processing device 1200 theoperating system 1212 may conduct an automatic process to trigger thedistance sensing in the background or foreground. Distance sensing maybe conducted periodically or continuously.

FIG. 12B shows one example of a distance sensing scenario. In theillustrated example, the distance sensor 1210 uses a transceiver 1208 toemit an electromagnetic beam 1202 in the direction of the user 1218.Thus, the transceiver 1202 might be positioned on a front facing surfaceof the data processing device 1200 (FIG. 12A). The electromagnetic beam1202 may impact the user 1218 and be reflected/scattered from the user1218 as a return electromagnetic beam 1204. The return electromagneticbeam 1204 may be analyzed by, for example, the processor 1224 (FIG. 12A)and/or the post-processing engine 1214 (FIG. 12A) to determine thedistance 1206 between the user 1218 and the display unit 1228 (FIG.12A). The distance 1206 may be used to adjust the display resolutionsetting 1216.

Display Layers

Turning now to FIG. 13, a display system 1300 is shown in which cascadeddisplay layers 1361, 1362 and 1363 are used to achieve spatial/temporalsuper-resolution in a display assembly 1360. In the illustrated example,a processor 1310 provides original graphics data 1334 (e.g., videoframes, still images), to the system 1300 via a bus 1320. A cascadeddisplay program 1331 may be stored in a memory 1330, wherein thecascaded display program 1331 may be part of a display driver associatedwith the display assembly 1360. The illustrated memory 1330 alsoincludes the original graphics data 1334 and factorized graphics data1335. In one example, the cascaded display program 1331 includes atemporal factorization component 1332 and a spatial factorizationcomponent 1333. The temporal factorization component 1332 may performtemporal factorization computation and the spatial factorizationcomponent may perform spatial factorization computation. The cascadeddisplay program 1331 may derive the factorized graphics data 1335 forpresentation on each display layer 1361, 1362 and 1363 based on userconfigurations and the original graphics data 1334.

The display assembly 1360 may be implemented as an LCD (liquid crystaldisplay) used in, for example, a head mounted display (HMD) application.More particularly, the display assembly 1360 may include a stack of LCDpanels interface boards a lens attachment, and so forth. Each panel maybe operated at a native resolution of, for example, 1280×800 pixels andwith a 60 Hz refresh rate. Other native resolutions, refresh rates,display panel technology and/or layer configurations may be used.

Multiple Display Units

FIG. 14 shows a graphics display system 1400 that includes a set ofdisplay units 1430 (1430 a-1430 n) that may generally be used to outputa widescreen (e.g., panoramic) presentation 1440 that includescoordinated content in a cohesive and structured topological form. Inthe illustrated example, a data processing device 1418 includes aprocessor 1415 that applies a logic function 1424 to hardware profiledata 1402 received from the set of display units 1430 over a network1420. The application of the logic function 1424 to the hardware profiledata 1402 may create a set of automatic topology settings 1406 when amatch of the hardware profile data with a set of settings in a hardwareprofile lookup table 1412 is not found. The illustrated set of automatictopology settings 1406 are transmitted from the display processingdevice 1418 to the display units 1430 over the network 1420.

The processor 1415 may perform and execute the logic function 1424 uponreceipt of the logic function 1424 from a display driver 1410. In thisregard, the display driver 1410 may include an auto topology module 1408that automatically configures and structures the topologies of thedisplay units 1432 to create the presentation 1440. In one example, thedisplay driver 1410 is a set of instructions, which when executed by theprocessor 1415, cause the data processing device 1418 to communicatewith the display units 1430, video cards, etc., and conduct automatictopology generation operations.

The data processing device 1418 may include, for example, a server,desktop, notebook computer, tablet computer, convertible tablet, MID,PDA, wearable device, media player, and so forth. Thus, the displayprocessing device 1418 may include a hardware control module 1416, astorage device 1414, random access memory (RAM, not shown), controllercards including one or more video controller cards, and so forth. In oneexample, the display units 1430 are flat-panel displays (e.g., liquidcrystal, active matrix, plasma, etc.), HMD's, video projection devices,and so forth, that coordinate with one another to produce thepresentation 1440. Moreover, the presentation 1440 may be generatedbased on a media file stored in the storage device 1414, wherein themedia file might include, for example, a film, video clip, animation,advertisement, etc., or any combination thereof.

The term “topology” may be considered the number, scaling, shape and/orother configuration parameter of a first display unit 1430 a, a seconddisplay unit 1430 b, a third display unit 1430 n, and so forth.Accordingly, the topology of the display units 1430 may enable thepresentation 1440 be visually presented in concert such that theindividual sections of the presentation 1440 are proportional andcompatible with the original dimensions and scope of the media beingplayed through the display units 1430. Thus, the topology may constitutespatial relations and/or geometric properties that are not impacted bythe continuous change of shape or size of the content rendered in thepresentation 1440. In one example, the auto topology module 1408includes a timing module 1426, a control module 1428, a signal monitormodule 1432 and a signal display module 1434. The timing module 1426 maydesignate a particular display unit in the set of display units 1430 asa sample display unit. In such a case, the timing module 1426 maydesignate the remaining display units 1430 as additional display units.In one example, the timing module 1426 automatically sets a shapingfactor to be compatible with the hardware profile data 1402, wherein thepresentation 1440 is automatically initiated by a sequence of graphicssignals 1422.

In one example, the control module 1428 modifies the set of automatictopology settings 1406. Additionally, the signal monitor module 1432 mayautomatically monitor the sequence of graphics signals 1422 and triggerthe storage device 1414 to associate the set of automatic topologysettings 1406 with the hardware profile lookup table 1412. Moreover, thesignal monitor module 1432 may automatically detect changes in the setof display units 1430 according to a set of change criteria andautomatically generate a new topology profile corresponding to thechange in the set of display units 1430. Thus, the new topology profilemay be applied to the set of display units 1430. The signal monitormodule 1432 may also trigger the signal display module 1434 to reapplythe set of automatic apology settings 1406 if the sequence of graphicssignals 1422 fails to meet a set of criteria. If the hardware profiledata 1402 does not support automatic topology display of the sequence ofgraphics signals 1422, the data processing device 1418 may report anerror and record the error in an error log 1413.

Cloud-Assisted Media Delivery

Turning now to FIG. 15, a cloud gaming system 1500 includes a client1540 that is coupled to a server 1520 through a network 1510. The client1540 may generally be a consumer of graphics (e.g., gaming, virtualreality/VR, augmented reality/AR) content that is housed, processed andrendered on the server 1520. The illustrated server 1520, which may bescalable, has the capacity to provide the graphics content to multipleclients simultaneously (e.g., by leveraging parallel and apportionedprocessing and rendering resources). In one example, the scalability ofthe server 1520 is limited by the capacity of the network 1510.Accordingly, there may be some threshold number of clients above whichthe service to all clients made degrade.

In one example, the server 1520 includes a graphics processor (e.g.,GPU) 1530, a host processor (e.g., CPU) 1524 and a network interfacecard (NIC) 1522. The NIC 1522 may receive a request from the client 1540for graphics content. The request from the client 1540 may cause thegraphics content to be retrieved from memory via an applicationexecuting on the host processor 1524. The host processor 1524 may carryout high level operations such as, for example, determining position,collision and motion of objects in a given scene. Based on the highlevel operations, the host processor 1524 may generate renderingcommands that are combined with the scene data and executed by thegraphics processor 1530. The rendering commands may cause the graphicsprocessor 1530 to define scene geometry, shading, lighting, motion,texturing, camera parameters, etc., for scenes to be presented via theclient 1540.

More particularly, the illustrated graphics processor 1530 includes agraphics renderer 1532 that executes rendering procedures according tothe rendering commands generated by the host processor 1524. The outputof the graphics renderer 1532 may be a stream of raw video frames thatare provided to a frame capturer 1534. The illustrated frame capturer1534 is coupled to an encoder 1536, which may compress/format the rawvideo stream for transmission over the network 1510. The encoder 1536may use a wide variety of video compression algorithms such as, forexample, the H.264 standard from the International TelecommunicationUnion Telecommunication Standardization Sector (ITUT), the MPEG4Advanced Video Coding (AVC) Standard from the International Organizationfor the Standardization/International Electrotechnical Commission(ISO/IEC), and so forth.

The illustrated client 1540, which may be a desktop computer, notebookcomputer, tablet computer, convertible tablet, wearable device, MID,PDA, media player, etc., includes an NIC 1542 to receive the transmittedvideo stream from the server 1520. The NIC 1522, may include thephysical layer and the basis for the software layer of the networkinterface in the client 1540 in order to facilitate communications overthe network 1510. The client 1540 may also include a decoder 1544 thatemploys the same formatting/compression scheme of the encoder 1536.Thus, the decompressed video stream may be provided from the decoder1544 to a video renderer 1546. The illustrated video renderer 1546 iscoupled to a display 1548 that visually presents the graphics content.

As already noted, the graphics content may include gaming content. Inthis regard, the client 1540 may conduct real-time interactive streamingthat involves the collection of user input from an input device 1550 anddelivery of the user input to the server 1520 via the network 1510. Thisreal-time interactive component of cloud gaming may pose challenges withregard to latency.

Additional System Overview Example

FIG. 16 is a block diagram of a processing system 1600, according to anembodiment. In various embodiments the system 1600 includes one or moreprocessors 1602 and one or more graphics processors 1608, and may be asingle processor desktop system, a multiprocessor workstation system, ora server system having a large number of processors 1602 or processorcores 1607. In on embodiment, the system 1600 is a processing platformincorporated within a system-on-a-chip (SoC) integrated circuit for usein mobile, handheld, or embedded devices.

An embodiment of system 1600 can include, or be incorporated within aserver-based gaming platform, a game console, including a game and mediaconsole, a mobile gaming console, a handheld game console, or an onlinegame console. In some embodiments system 1600 is a mobile phone, smartphone, tablet computing device or mobile Internet device. Dataprocessing system 1600 can also include, couple with, or be integratedwithin a wearable device, such as a smart watch wearable device, smarteyewear device, augmented reality device, or virtual reality device. Insome embodiments, data processing system 1600 is a television or set topbox device having one or more processors 1602 and a graphical interfacegenerated by one or more graphics processors 1608.

In some embodiments, the one or more processors 1602 each include one ormore processor cores 1607 to process instructions which, when executed,perform operations for system and user software. In some embodiments,each of the one or more processor cores 1607 is configured to process aspecific instruction set 1609. In some embodiments, instruction set 1609may facilitate Complex Instruction Set Computing (CISC), ReducedInstruction Set Computing (RISC), or computing via a Very LongInstruction Word (VLIW). Multiple processor cores 1607 may each processa different instruction set 1609, which may include instructions tofacilitate the emulation of other instruction sets. Processor core 1607may also include other processing devices, such a Digital SignalProcessor (DSP).

In some embodiments, the processor 1602 includes cache memory 1604.Depending on the architecture, the processor 1602 can have a singleinternal cache or multiple levels of internal cache. In someembodiments, the cache memory is shared among various components of theprocessor 1602. In some embodiments, the processor 1602 also uses anexternal cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC))(not shown), which may be shared among processor cores 1607 using knowncache coherency techniques. A register file 1606 is additionallyincluded in processor 1602 which may include different types ofregisters for storing different types of data (e.g., integer registers,floating point registers, status registers, and an instruction pointerregister). Some registers may be general-purpose registers, while otherregisters may be specific to the design of the processor 1602.

In some embodiments, processor 1602 is coupled to a processor bus 1610to transmit communication signals such as address, data, or controlsignals between processor 1602 and other components in system 1600. Inone embodiment the system 1600 uses an exemplary ‘hub’ systemarchitecture, including a memory controller hub 1616 and an Input Output(I/O) controller hub 1630. A memory controller hub 1616 facilitatescommunication between a memory device and other components of system1600, while an I/O Controller Hub (ICH) 1630 provides connections to I/Odevices via a local I/O bus. In one embodiment, the logic of the memorycontroller hub 1616 is integrated within the processor.

Memory device 1620 can be a dynamic random access memory (DRAM) device,a static random access memory (SRAM) device, flash memory device,phase-change memory device, or some other memory device having suitableperformance to serve as process memory. In one embodiment the memorydevice 1620 can operate as system memory for the system 1600, to storedata 1622 and instructions 1621 for use when the one or more processors1602 executes an application or process. Memory controller hub 1616 alsocouples with an optional external graphics processor 1612, which maycommunicate with the one or more graphics processors 1608 in processors1602 to perform graphics and media operations.

In some embodiments, ICH 1630 enables peripherals to connect to memorydevice 1620 and processor 1602 via a high-speed I/O bus. The I/Operipherals include, but are not limited to, an audio controller 1646, afirmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi,Bluetooth), a data storage device 1624 (e.g., hard disk drive, flashmemory, etc.), and a legacy I/O controller 1640 for coupling legacy(e.g., Personal System 2 (PS/2)) devices to the system. One or moreUniversal Serial Bus (USB) controllers 1642 connect input devices, suchas keyboard and mouse 1644 combinations. A network controller 1634 mayalso couple to ICH 1630. In some embodiments, a high-performance networkcontroller (not shown) couples to processor bus 1610. It will beappreciated that the system 1600 shown is exemplary and not limiting, asother types of data processing systems that are differently configuredmay also be used. For example, the I/O controller hub 1630 may beintegrated within the one or more processor 1602, or the memorycontroller hub 1616 and I/O controller hub 1630 may be integrated into adiscreet external graphics processor, such as the external graphicsprocessor 1612.

FIG. 17 is a block diagram of an embodiment of a processor 1700 havingone or more processor cores 1702A-1702N, an integrated memory controller1714, and an integrated graphics processor 1708. Those elements of FIG.17 having the same reference numbers (or names) as the elements of anyother figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such. Processor1700 can include additional cores up to and including additional core1702N represented by the dashed lined boxes. Each of processor cores1702A-1702N includes one or more internal cache units 1704A-1704N. Insome embodiments each processor core also has access to one or moreshared cached units 1706.

The internal cache units 1704A-1704N and shared cache units 1706represent a cache memory hierarchy within the processor 1700. The cachememory hierarchy may include at least one level of instruction and datacache within each processor core and one or more levels of sharedmid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), orother levels of cache, where the highest level of cache before externalmemory is classified as the LLC. In some embodiments, cache coherencylogic maintains coherency between the various cache units 1706 and1704A-1704N.

In some embodiments, processor 1700 may also include a set of one ormore bus controller units 1716 and a system agent core 1710. The one ormore bus controller units 1716 manage a set of peripheral buses, such asone or more Peripheral Component Interconnect buses (e.g., PCI, PCIExpress). System agent core 1710 provides management functionality forthe various processor components. In some embodiments, system agent core1710 includes one or more integrated memory controllers 1714 to manageaccess to various external memory devices (not shown).

In some embodiments, one or more of the processor cores 1702A-1702Ninclude support for simultaneous multi-threading. In such embodiment,the system agent core 1710 includes components for coordinating andoperating cores 1702A-1702N during multi-threaded processing. Systemagent core 1710 may additionally include a power control unit (PCU),which includes logic and components to regulate the power state ofprocessor cores 1702A-1702N and graphics processor 1708.

In some embodiments, processor 1700 additionally includes graphicsprocessor 1708 to execute graphics processing operations. In someembodiments, the graphics processor 1708 couples with the set of sharedcache units 1706, and the system agent core 1710, including the one ormore integrated memory controllers 1714. In some embodiments, a displaycontroller 1711 is coupled with the graphics processor 1708 to drivegraphics processor output to one or more coupled displays. In someembodiments, display controller 1711 may be a separate module coupledwith the graphics processor via at least one interconnect, or may beintegrated within the graphics processor 1708 or system agent core 1710.

In some embodiments, a ring based interconnect unit 1712 is used tocouple the internal components of the processor 1700. However, analternative interconnect unit may be used, such as a point-to-pointinterconnect, a switched interconnect, or other techniques, includingtechniques well known in the art. In some embodiments, graphicsprocessor 1708 couples with the ring interconnect 1712 via an I/O link1713.

The exemplary I/O link 1713 represents at least one of multiplevarieties of I/O interconnects, including an on package I/O interconnectwhich facilitates communication between various processor components anda high-performance embedded memory module 1718, such as an eDRAM module.In some embodiments, each of the processor cores 1702-1702N and graphicsprocessor 1708 use embedded memory modules 1718 as a shared Last LevelCache.

In some embodiments, processor cores 1702A-1702N are homogenous coresexecuting the same instruction set architecture. In another embodiment,processor cores 1702A-1702N are heterogeneous in terms of instructionset architecture (ISA), where one or more of processor cores 1702A-Nexecute a first instruction set, while at least one of the other coresexecutes a subset of the first instruction set or a differentinstruction set. In one embodiment processor cores 1702A-1702N areheterogeneous in terms of microarchitecture, where one or more coreshaving a relatively higher power consumption couple with one or morepower cores having a lower power consumption. Additionally, processor1700 can be implemented on one or more chips or as an SoC integratedcircuit having the illustrated components, in addition to othercomponents.

FIG. 18 is a block diagram of a graphics processor 1800, which may be adiscrete graphics processing unit, or may be a graphics processorintegrated with a plurality of processing cores. In some embodiments,the graphics processor communicates via a memory mapped I/O interface toregisters on the graphics processor and with commands placed into theprocessor memory. In some embodiments, graphics processor 1800 includesa memory interface 1814 to access memory. Memory interface 1814 can bean interface to local memory, one or more internal caches, one or moreshared external caches, and/or to system memory.

In some embodiments, graphics processor 1800 also includes a displaycontroller 1802 to drive display output data to a display device 1820.Display controller 1802 includes hardware for one or more overlay planesfor the display and composition of multiple layers of video or userinterface elements. In some embodiments, graphics processor 1800includes a video codec engine 1806 to encode, decode, or transcode mediato, from, or between one or more media encoding formats, including, butnot limited to Moving Picture Experts Group (MPEG) formats such asMPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, aswell as the Society of Motion Picture & Television Engineers (SMPTE)421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such asJPEG, and Motion JPEG (MJPEG) formats.

In some embodiments, graphics processor 1800 includes a block imagetransfer (BLIT) engine 1804 to perform two-dimensional (2D) rasterizeroperations including, for example, bit-boundary block transfers.However, in one embodiment, 2D graphics operations are performed usingone or more components of graphics processing engine (GPE) 1810. In someembodiments, graphics processing engine 1810 is a compute engine forperforming graphics operations, including three-dimensional (3D)graphics operations and media operations.

In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing3D operations, such as rendering three-dimensional images and scenesusing processing functions that act upon 3D primitive shapes (e.g.,rectangle, triangle, etc.). The 3D pipeline 1812 includes programmableand fixed function elements that perform various tasks within theelement and/or spawn execution threads to a 3D/Media sub-system 1815.While 3D pipeline 1812 can be used to perform media operations, anembodiment of GPE 1810 also includes a media pipeline 1816 that isspecifically used to perform media operations, such as videopost-processing and image enhancement.

In some embodiments, media pipeline 1816 includes fixed function orprogrammable logic units to perform one or more specialized mediaoperations, such as video decode acceleration, video de-interlacing, andvideo encode acceleration in place of, or on behalf of video codecengine 1806. In some embodiments, media pipeline 1816 additionallyincludes a thread spawning unit to spawn threads for execution on3D/Media sub-system 1815. The spawned threads perform computations forthe media operations on one or more graphics execution units included in3D/Media sub-system 1815.

In some embodiments, 3D/Media subsystem 1815 includes logic forexecuting threads spawned by 3D pipeline 1812 and media pipeline 1816.In one embodiment, the pipelines send thread execution requests to3D/Media subsystem 1815, which includes thread dispatch logic forarbitrating and dispatching the various requests to available threadexecution resources. The execution resources include an array ofgraphics execution units to process the 3D and media threads. In someembodiments, 3D/Media subsystem 1815 includes one or more internalcaches for thread instructions and data. In some embodiments, thesubsystem also includes shared memory, including registers andaddressable memory, to share data between threads and to store outputdata.

3D/Media Processing

FIG. 19 is a block diagram of a graphics processing engine 1910 of agraphics processor in accordance with some embodiments. In oneembodiment, the GPE 1910 is a version of the GPE 1810 shown in FIG. 18.Elements of FIG. 19 having the same reference numbers (or names) as theelements of any other figure herein can operate or function in anymanner similar to that described elsewhere herein, but are not limitedto such.

In some embodiments, GPE 1910 couples with a command streamer 1903,which provides a command stream to the GPE 3D and media pipelines 1912,1916. In some embodiments, command streamer 1903 is coupled to memory,which can be system memory, or one or more of internal cache memory andshared cache memory. In some embodiments, command streamer 1903 receivescommands from the memory and sends the commands to 3D pipeline 1912and/or media pipeline 1916. The commands are directives fetched from aring buffer, which stores commands for the 3D and media pipelines 1912,1916. In one embodiment, the ring buffer can additionally include batchcommand buffers storing batches of multiple commands. The 3D and mediapipelines 1912, 1916 process the commands by performing operations vialogic within the respective pipelines or by dispatching one or moreexecution threads to an execution unit array 1914. In some embodiments,execution unit array 1914 is scalable, such that the array includes avariable number of execution units based on the target power andperformance level of GPE 1910.

In some embodiments, a sampling engine 1930 couples with memory (e.g.,cache memory or system memory) and execution unit array 1914. In someembodiments, sampling engine 1930 provides a memory access mechanism forexecution unit array 1914 that allows execution array 1914 to readgraphics and media data from memory. In some embodiments, samplingengine 1930 includes logic to perform specialized image samplingoperations for media.

In some embodiments, the specialized media sampling logic in samplingengine 1930 includes a de-noise/de-interlace module 1932, a motionestimation module 1934, and an image scaling and filtering module 1936.In some embodiments, de-noise/de-interlace module 1932 includes logic toperform one or more of a de-noise or a de-interlace algorithm on decodedvideo data. The de-interlace logic combines alternating fields ofinterlaced video content into a single fame of video. The de-noise logicreduces or removes data noise from video and image data. In someembodiments, the de-noise logic and de-interlace logic are motionadaptive and use spatial or temporal filtering based on the amount ofmotion detected in the video data. In some embodiments, thede-noise/de-interlace module 1932 includes dedicated motion detectionlogic (e.g., within the motion estimation engine 1934).

In some embodiments, motion estimation engine 1934 provides hardwareacceleration for video operations by performing video accelerationfunctions such as motion vector estimation and prediction on video data.The motion estimation engine determines motion vectors that describe thetransformation of image data between successive video frames. In someembodiments, a graphics processor media codec uses video motionestimation engine 1934 to perform operations on video at the macro-blocklevel that may otherwise be too computationally intensive to performwith a general-purpose processor. In some embodiments, motion estimationengine 1934 is generally available to graphics processor components toassist with video decode and processing functions that are sensitive oradaptive to the direction or magnitude of the motion within video data.

In some embodiments, image scaling and filtering module 1936 performsimage-processing operations to enhance the visual quality of generatedimages and video. In some embodiments, scaling and filtering module 1936processes image and video data during the sampling operation beforeproviding the data to execution unit array 1914.

In some embodiments, the GPE 1910 includes a data port 1944, whichprovides an additional mechanism for graphics subsystems to accessmemory. In some embodiments, data port 1944 facilitates memory accessfor operations including render target writes, constant buffer reads,scratch memory space reads/writes, and media surface accesses. In someembodiments, data port 1944 includes cache memory space to cacheaccesses to memory. The cache memory can be a single data cache orseparated into multiple caches for the multiple subsystems that accessmemory via the data port (e.g., a render buffer cache, a constant buffercache, etc.). In some embodiments, threads executing on an executionunit in execution unit array 1914 communicate with the data port byexchanging messages via a data distribution interconnect that coupleseach of the sub-systems of GPE 1910.

Execution Units

FIG. 20 is a block diagram of another embodiment of a graphics processor2000. Elements of FIG. 20 having the same reference numbers (or names)as the elements of any other figure herein can operate or function inany manner similar to that described elsewhere herein, but are notlimited to such.

In some embodiments, graphics processor 2000 includes a ringinterconnect 2002, a pipeline front-end 2004, a media engine 2037, andgraphics cores 2080A-2080N. In some embodiments, ring interconnect 2002couples the graphics processor to other processing units, includingother graphics processors or one or more general-purpose processorcores. In some embodiments, the graphics processor is one of manyprocessors integrated within a multi-core processing system.

In some embodiments, graphics processor 2000 receives batches ofcommands via ring interconnect 2002. The incoming commands areinterpreted by a command streamer 2003 in the pipeline front-end 2004.In some embodiments, graphics processor 2000 includes scalable executionlogic to perform 3D geometry processing and media processing via thegraphics core(s) 2080A-2080N. For 3D geometry processing commands,command streamer 2003 supplies commands to geometry pipeline 2036. Forat least some media processing commands, command streamer 2003 suppliesthe commands to a video front end 2034, which couples with a mediaengine 2037. In some embodiments, media engine 2037 includes a VideoQuality Engine (VQE) 2030 for video and image post-processing and amulti-format encode/decode (MFX) 2033 engine to providehardware-accelerated media data encode and decode. In some embodiments,geometry pipeline 2036 and media engine 2037 each generate executionthreads for the thread execution resources provided by at least onegraphics core 2080A.

In some embodiments, graphics processor 2000 includes scalable threadexecution resources featuring modular cores 2080A-2080N (sometimesreferred to as core slices), each having multiple sub-cores 2050A-2050N,2060A-2060N (sometimes referred to as core sub-slices). In someembodiments, graphics processor 2000 can have any number of graphicscores 2080A through 2080N. In some embodiments, graphics processor 2000includes a graphics core 2080A having at least a first sub-core 2050Aand a second core sub-core 2060A. In other embodiments, the graphicsprocessor is a low power processor with a single sub-core (e.g., 2050A).In some embodiments, graphics processor 2000 includes multiple graphicscores 2080A-2080N, each including a set of first sub-cores 2050A-2050Nand a set of second sub-cores 2060A-2060N. Each sub-core in the set offirst sub-cores 2050A-2050N includes at least a first set of executionunits 2052A-2052N and media/texture samplers 2054A-2054N. Each sub-corein the set of second sub-cores 2060A-2060N includes at least a secondset of execution units 2062A-2062N and samplers 2064A-2064N. In someembodiments, each sub-core 2050A-2050N, 2060A-2060N shares a set ofshared resources 2070A-2070N. In some embodiments, the shared resourcesinclude shared cache memory and pixel operation logic. Other sharedresources may also be included in the various embodiments of thegraphics processor.

FIG. 21 illustrates thread execution logic 2100 including an array ofprocessing elements employed in some embodiments of a GPE. Elements ofFIG. 21 having the same reference numbers (or names) as the elements ofany other figure herein can operate or function in any manner similar tothat described elsewhere herein, but are not limited to such.

In some embodiments, thread execution logic 2100 includes a pixel shader2102, a thread dispatcher 2104, instruction cache 2106, a scalableexecution unit array including a plurality of execution units2108A-2108N, a sampler 2110, a data cache 2112, and a data port 2114. Inone embodiment the included components are interconnected via aninterconnect fabric that links to each of the components. In someembodiments, thread execution logic 2100 includes one or moreconnections to memory, such as system memory or cache memory, throughone or more of instruction cache 2106, data port 2114, sampler 2110, andexecution unit array 2108A-2108N. In some embodiments, each executionunit (e.g. 2108A) is an individual vector processor capable of executingmultiple simultaneous threads and processing multiple data elements inparallel for each thread. In some embodiments, execution unit array2108A-2108N includes any number individual execution units.

In some embodiments, execution unit array 2108A-2108N is primarily usedto execute “shader” programs. In some embodiments, the execution unitsin array 2108A-2108N execute an instruction set that includes nativesupport for many standard 3D graphics shader instructions, such thatshader programs from graphics libraries (e.g., Direct 3D and OpenGL) areexecuted with a minimal translation. The execution units support vertexand geometry processing (e.g., vertex programs, geometry programs,vertex shaders), pixel processing (e.g., pixel shaders, fragmentshaders) and general-purpose processing (e.g., compute and mediashaders).

Each execution unit in execution unit array 2108A-2108N operates onarrays of data elements. The number of data elements is the “executionsize,” or the number of channels for the instruction. An executionchannel is a logical unit of execution for data element access, masking,and flow control within instructions. The number of channels may beindependent of the number of physical Arithmetic Logic Units (ALUs) orFloating Point Units (FPUs) for a particular graphics processor. In someembodiments, execution units 2108A-2108N support integer andfloating-point data types.

The execution unit instruction set includes single instruction multipledata (SIMD) instructions. The various data elements can be stored as apacked data type in a register and the execution unit will process thevarious elements based on the data size of the elements. For example,when operating on a 256-bit wide vector, the 256 bits of the vector arestored in a register and the execution unit operates on the vector asfour separate 64-bit packed data elements (Quad-Word (QW) size dataelements), eight separate 32-bit packed data elements (Double Word (DW)size data elements), sixteen separate 16-bit packed data elements (Word(W) size data elements), or thirty-two separate 8-bit data elements(byte (B) size data elements). However, different vector widths andregister sizes are possible.

One or more internal instruction caches (e.g., 2106) are included in thethread execution logic 2100 to cache thread instructions for theexecution units. In some embodiments, one or more data caches (e.g.,2112) are included to cache thread data during thread execution. In someembodiments, sampler 2110 is included to provide texture sampling for 3Doperations and media sampling for media operations. In some embodiments,sampler 2110 includes specialized texture or media samplingfunctionality to process texture or media data during the samplingprocess before providing the sampled data to an execution unit.

During execution, the graphics and media pipelines send threadinitiation requests to thread execution logic 2100 via thread spawningand dispatch logic. In some embodiments, thread execution logic 2100includes a local thread dispatcher 2104 that arbitrates threadinitiation requests from the graphics and media pipelines andinstantiates the requested threads on one or more execution units2108A-2108N. For example, the geometry pipeline (e.g., 2036 of FIG. 20)dispatches vertex processing, tessellation, or geometry processingthreads to thread execution logic 2100 (FIG. 21). In some embodiments,thread dispatcher 2104 can also process runtime thread spawning requestsfrom the executing shader programs.

Once a group of geometric objects has been processed and rasterized intopixel data, pixel shader 2102 is invoked to further compute outputinformation and cause results to be written to output surfaces (e.g.,color buffers, depth buffers, stencil buffers, etc.). In someembodiments, pixel shader 2102 calculates the values of the variousvertex attributes that are to be interpolated across the rasterizedobject. In some embodiments, pixel shader 2102 then executes anapplication programming interface (API)-supplied pixel shader program.To execute the pixel shader program, pixel shader 2102 dispatchesthreads to an execution unit (e.g., 2108A) via thread dispatcher 2104.In some embodiments, pixel shader 2102 uses texture sampling logic insampler 2110 to access texture data in texture maps stored in memory.Arithmetic operations on the texture data and the input geometry datacompute pixel color data for each geometric fragment, or discards one ormore pixels from further processing.

In some embodiments, the data port 2114 provides a memory accessmechanism for the thread execution logic 2100 output processed data tomemory for processing on a graphics processor output pipeline. In someembodiments, the data port 2114 includes or couples to one or more cachememories (e.g., data cache 2112) to cache data for memory access via thedata port.

FIG. 22 is a block diagram illustrating a graphics processor instructionformats 2200 according to some embodiments. In one or more embodiment,the graphics processor execution units support an instruction set havinginstructions in multiple formats. The solid lined boxes illustrate thecomponents that are generally included in an execution unit instruction,while the dashed lines include components that are optional or that areonly included in a sub-set of the instructions. In some embodiments,instruction format 2200 described and illustrated aremacro-instructions, in that they are instructions supplied to theexecution unit, as opposed to micro-operations resulting frominstruction decode once the instruction is processed.

In some embodiments, the graphics processor execution units nativelysupport instructions in a 128-bit format 2210. A 64-bit compactedinstruction format 2230 is available for some instructions based on theselected instruction, instruction options, and number of operands. Thenative 128-bit format 2210 provides access to all instruction options,while some options and operations are restricted in the 64-bit format2230. The native instructions available in the 64-bit format 2230 varyby embodiment. In some embodiments, the instruction is compacted in partusing a set of index values in an index field 2213. The execution unithardware references a set of compaction tables based on the index valuesand uses the compaction table outputs to reconstruct a nativeinstruction in the 128-bit format 2210.

For each format, instruction opcode 2212 defines the operation that theexecution unit is to perform. The execution units execute eachinstruction in parallel across the multiple data elements of eachoperand. For example, in response to an add instruction the executionunit performs a simultaneous add operation across each color channelrepresenting a texture element or picture element. By default, theexecution unit performs each instruction across all data channels of theoperands. In some embodiments, instruction control field 2214 enablescontrol over certain execution options, such as channels selection(e.g., predication) and data channel order (e.g., swizzle). For 128-bitinstructions 2210 an exec-size field 2216 limits the number of datachannels that will be executed in parallel. In some embodiments,exec-size field 2216 is not available for use in the 64-bit compactinstruction format 2230.

Some execution unit instructions have up to three operands including twosource operands, src0 2220, src1 2222, and one destination 2218. In someembodiments, the execution units support dual destination instructions,where one of the destinations is implied. Data manipulation instructionscan have a third source operand (e.g., SRC2 2224), where the instructionopcode 2212 determines the number of source operands. An instruction'slast source operand can be an immediate (e.g., hard-coded) value passedwith the instruction.

In some embodiments, the 128-bit instruction format 2210 includes anaccess/address mode information 2226 specifying, for example, whetherdirect register addressing mode or indirect register addressing mode isused. When direct register addressing mode is used, the register addressof one or more operands is directly provided by bits in the instruction2210.

In some embodiments, the 128-bit instruction format 2210 includes anaccess/address mode field 2226, which specifies an address mode and/oran access mode for the instruction. In one embodiment the access mode todefine a data access alignment for the instruction. Some embodimentssupport access modes including a 16-byte aligned access mode and a1-byte aligned access mode, where the byte alignment of the access modedetermines the access alignment of the instruction operands. Forexample, when in a first mode, the instruction 2210 may use byte-alignedaddressing for source and destination operands and when in a secondmode, the instruction 2210 may use 16-byte-aligned addressing for allsource and destination operands.

In one embodiment, the address mode portion of the access/address modefield 2226 determines whether the instruction is to use direct orindirect addressing. When direct register addressing mode is used bitsin the instruction 2210 directly provide the register address of one ormore operands. When indirect register addressing mode is used, theregister address of one or more operands may be computed based on anaddress register value and an address immediate field in theinstruction.

In some embodiments instructions are grouped based on opcode 2212bit-fields to simplify Opcode decode 2240. For an 8-bit opcode, bits 4,5, and 6 allow the execution unit to determine the type of opcode. Theprecise opcode grouping shown is merely an example. In some embodiments,a move and logic opcode group 2242 includes data movement and logicinstructions (e.g., move (mov), compare (cmp)). In some embodiments,move and logic group 2242 shares the five most significant bits (MSB),where move (mov) instructions are in the form of 0000xxxxb and logicinstructions are in the form of 0001xxxxb. A flow control instructiongroup 2244 (e.g., call, jump (jmp)) includes instructions in the form of0010xxxxb (e.g., 0x20). A miscellaneous instruction group 2246 includesa mix of instructions, including synchronization instructions (e.g.,wait, send) in the form of 0011xxxxb (e.g., 0x30). A parallel mathinstruction group 2248 includes component-wise arithmetic instructions(e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). Theparallel math group 2248 performs the arithmetic operations in parallelacross data channels. The vector math group 2250 includes arithmeticinstructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). Thevector math group performs arithmetic such as dot product calculationson vector operands.

Graphics Pipeline

FIG. 23 is a block diagram of another embodiment of a graphics processor2300. Elements of FIG. 23 having the same reference numbers (or names)as the elements of any other figure herein can operate or function inany manner similar to that described elsewhere herein, but are notlimited to such.

In some embodiments, graphics processor 2300 includes a graphicspipeline 2320, a media pipeline 2330, a display engine 2340, threadexecution logic 2350, and a render output pipeline 2370. In someembodiments, graphics processor 2300 is a graphics processor within amulti-core processing system that includes one or more general purposeprocessing cores. The graphics processor is controlled by registerwrites to one or more control registers (not shown) or via commandsissued to graphics processor 2300 via a ring interconnect 2302. In someembodiments, ring interconnect 2302 couples graphics processor 2300 toother processing components, such as other graphics processors orgeneral-purpose processors. Commands from ring interconnect 2302 areinterpreted by a command streamer 2303, which supplies instructions toindividual components of graphics pipeline 2320 or media pipeline 2330.

In some embodiments, command streamer 2303 directs the operation of avertex fetcher 2305 that reads vertex data from memory and executesvertex-processing commands provided by command streamer 2303. In someembodiments, vertex fetcher 2305 provides vertex data to a vertex shader2307, which performs coordinate space transformation and lightingoperations to each vertex. In some embodiments, vertex fetcher 2305 andvertex shader 2307 execute vertex-processing instructions by dispatchingexecution threads to execution units 2352A, 2352B via a threaddispatcher 2331.

In some embodiments, execution units 2352A, 2352B are an array of vectorprocessors having an instruction set for performing graphics and mediaoperations. In some embodiments, execution units 2352A, 2352B have anattached L1 cache 2351 that is specific for each array or shared betweenthe arrays. The cache can be configured as a data cache, an instructioncache, or a single cache that is partitioned to contain data andinstructions in different partitions.

In some embodiments, graphics pipeline 2320 includes tessellationcomponents to perform hardware-accelerated tessellation of 3D objects.In some embodiments, a programmable hull shader 2311 configures thetessellation operations. A programmable domain shader 2317 providesback-end evaluation of tessellation output. A tessellator 2313 operatesat the direction of hull shader 2311 and contains special purpose logicto generate a set of detailed geometric objects based on a coarsegeometric model that is provided as input to graphics pipeline 2320. Insome embodiments, if tessellation is not used, tessellation components2311, 2313, 2317 can be bypassed.

In some embodiments, complete geometric objects can be processed by ageometry shader 2319 via one or more threads dispatched to executionunits 2352A, 2352B, or can proceed directly to the clipper 2329. In someembodiments, the geometry shader operates on entire geometric objects,rather than vertices or patches of vertices as in previous stages of thegraphics pipeline. If the tessellation is disabled the geometry shader2319 receives input from the vertex shader 2307. In some embodiments,geometry shader 2319 is programmable by a geometry shader program toperform geometry tessellation if the tessellation units are disabled.

Before rasterization, a clipper 2329 processes vertex data. The clipper2329 may be a fixed function clipper or a programmable clipper havingclipping and geometry shader functions. In some embodiments, arasterizer 2373 (e.g., depth test component) in the render outputpipeline 2370 dispatches pixel shaders to convert the geometric objectsinto their per pixel representations. In some embodiments, pixel shaderlogic is included in thread execution logic 2350. In some embodiments,an application can bypass the rasterizer 2373 and access un-rasterizedvertex data via a stream out unit 2323.

The graphics processor 2300 has an interconnect bus, interconnectfabric, or some other interconnect mechanism that allows data andmessage passing amongst the major components of the processor. In someembodiments, execution units 2352A, 2352B and associated cache(s) 2351,texture and media sampler 2354, and texture/sampler cache 2358interconnect via a data port 2356 to perform memory access andcommunicate with render output pipeline components of the processor. Insome embodiments, sampler 2354, caches 2351, 2358 and execution units2352A, 2352B each have separate memory access paths.

In some embodiments, render output pipeline 2370 contains a rasterizer2373 that converts vertex-based objects into an associated pixel-basedrepresentation. In some embodiments, the rasterizer logic includes awindower/masker unit to perform fixed function triangle and linerasterization. An associated render cache 2378 and depth cache 2379 arealso available in some embodiments. A pixel operations component 2377performs pixel-based operations on the data, though in some instances,pixel operations associated with 2D operations (e.g. bit block imagetransfers with blending) are performed by the 2D engine 2341, orsubstituted at display time by the display controller 2343 using overlaydisplay planes. In some embodiments, a shared L3 cache 2375 is availableto all graphics components, allowing the sharing of data without the useof main system memory.

In some embodiments, graphics processor media pipeline 2330 includes amedia engine 2337 and a video front end 2334. In some embodiments, videofront end 2334 receives pipeline commands from the command streamer2303. In some embodiments, media pipeline 2330 includes a separatecommand streamer. In some embodiments, video front-end 2334 processesmedia commands before sending the command to the media engine 2337. Insome embodiments, media engine 2337 includes thread spawningfunctionality to spawn threads for dispatch to thread execution logic2350 via thread dispatcher 2331.

In some embodiments, graphics processor 2300 includes a display engine2340. In some embodiments, display engine 2340 is external to processor2300 and couples with the graphics processor via the ring interconnect2302, or some other interconnect bus or fabric. In some embodiments,display engine 2340 includes a 2D engine 2341 and a display controller2343. In some embodiments, display engine 2340 contains special purposelogic capable of operating independently of the 3D pipeline. In someembodiments, display controller 2343 couples with a display device (notshown), which may be a system integrated display device, as in a laptopcomputer, or an external display device attached via a display deviceconnector.

In some embodiments, graphics pipeline 2320 and media pipeline 2330 areconfigurable to perform operations based on multiple graphics and mediaprogramming interfaces and are not specific to any one applicationprogramming interface (API). In some embodiments, driver software forthe graphics processor translates API calls that are specific to aparticular graphics or media library into commands that can be processedby the graphics processor. In some embodiments, support is provided forthe Open Graphics Library (OpenGL) and Open Computing Language (OpenCL)from the Khronos Group, the Direct3D library from the MicrosoftCorporation, or support may be provided to both OpenGL and D3D. Supportmay also be provided for the Open Source Computer Vision Library(OpenCV). A future API with a compatible 3D pipeline would also besupported if a mapping can be made from the pipeline of the future APIto the pipeline of the graphics processor.

Graphics Pipeline Programming

FIG. 24A is a block diagram illustrating a graphics processor commandformat 2400 according to some embodiments. FIG. 24B is a block diagramillustrating a graphics processor command sequence 2410 according to anembodiment. The solid lined boxes in FIG. 24A illustrate the componentsthat are generally included in a graphics command while the dashed linesinclude components that are optional or that are only included in asub-set of the graphics commands. The exemplary graphics processorcommand format 2400 of FIG. 24A includes data fields to identify atarget client 2402 of the command, a command operation code (opcode)2404, and the relevant data 2406 for the command. A sub-opcode 2405 anda command size 2408 are also included in some commands.

In some embodiments, client 2402 specifies the client unit of thegraphics device that processes the command data. In some embodiments, agraphics processor command parser examines the client field of eachcommand to condition the further processing of the command and route thecommand data to the appropriate client unit. In some embodiments, thegraphics processor client units include a memory interface unit, arender unit, a 2D unit, a 3D unit, and a media unit. Each client unithas a corresponding processing pipeline that processes the commands.Once the command is received by the client unit, the client unit readsthe opcode 2404 and, if present, sub-opcode 2405 to determine theoperation to perform. The client unit performs the command usinginformation in data field 2406. For some commands an explicit commandsize 2408 is expected to specify the size of the command. In someembodiments, the command parser automatically determines the size of atleast some of the commands based on the command opcode. In someembodiments commands are aligned via multiples of a double word.

The flow diagram in FIG. 24B shows an exemplary graphics processorcommand sequence 2410. In some embodiments, software or firmware of adata processing system that features an embodiment of a graphicsprocessor uses a version of the command sequence shown to set up,execute, and terminate a set of graphics operations. A sample commandsequence is shown and described for purposes of example only asembodiments are not limited to these specific commands or to thiscommand sequence. Moreover, the commands may be issued as batch ofcommands in a command sequence, such that the graphics processor willprocess the sequence of commands in at least partially concurrence.

In some embodiments, the graphics processor command sequence 2410 maybegin with a pipeline flush command 2412 to cause any active graphicspipeline to complete the currently pending commands for the pipeline. Insome embodiments, the 3D pipeline 2422 and the media pipeline 2424 donot operate concurrently. The pipeline flush is performed to cause theactive graphics pipeline to complete any pending commands. In responseto a pipeline flush, the command parser for the graphics processor willpause command processing until the active drawing engines completepending operations and the relevant read caches are invalidated.Optionally, any data in the render cache that is marked ‘dirty’ can beflushed to memory. In some embodiments, pipeline flush command 2412 canbe used for pipeline synchronization or before placing the graphicsprocessor into a low power state.

In some embodiments, a pipeline select command 2413 is used when acommand sequence requires the graphics processor to explicitly switchbetween pipelines. In some embodiments, a pipeline select command 2413is required only once within an execution context before issuingpipeline commands unless the context is to issue commands for bothpipelines. In some embodiments, a pipeline flush command is 2412 isrequired immediately before a pipeline switch via the pipeline selectcommand 2413.

In some embodiments, a pipeline control command 2414 configures agraphics pipeline for operation and is used to program the 3D pipeline2422 and the media pipeline 2424. In some embodiments, pipeline controlcommand 2414 configures the pipeline state for the active pipeline. Inone embodiment, the pipeline control command 2414 is used for pipelinesynchronization and to clear data from one or more cache memories withinthe active pipeline before processing a batch of commands.

In some embodiments, return buffer state commands 2416 are used toconfigure a set of return buffers for the respective pipelines to writedata. Some pipeline operations require the allocation, selection, orconfiguration of one or more return buffers into which the operationswrite intermediate data during processing. In some embodiments, thegraphics processor also uses one or more return buffers to store outputdata and to perform cross thread communication. In some embodiments, thereturn buffer state 2416 includes selecting the size and number ofreturn buffers to use for a set of pipeline operations.

The remaining commands in the command sequence differ based on theactive pipeline for operations. Based on a pipeline determination 2420,the command sequence is tailored to the 3D pipeline 2422 beginning withthe 3D pipeline state 2430, or the media pipeline 2424 beginning at themedia pipeline state 2440.

The commands for the 3D pipeline state 2430 include 3D state settingcommands for vertex buffer state, vertex element state, constant colorstate, depth buffer state, and other state variables that are to beconfigured before 3D primitive commands are processed. The values ofthese commands are determined at least in part based the particular 3DAPI in use. In some embodiments, 3D pipeline state 2430 commands arealso able to selectively disable or bypass certain pipeline elements ifthose elements will not be used.

In some embodiments, 3D primitive 2432 command is used to submit 3Dprimitives to be processed by the 3D pipeline. Commands and associatedparameters that are passed to the graphics processor via the 3Dprimitive 2432 command are forwarded to the vertex fetch function in thegraphics pipeline. The vertex fetch function uses the 3D primitive 2432command data to generate vertex data structures. The vertex datastructures are stored in one or more return buffers. In someembodiments, 3D primitive 2432 command is used to perform vertexoperations on 3D primitives via vertex shaders. To process vertexshaders, 3D pipeline 2422 dispatches shader execution threads tographics processor execution units.

In some embodiments, 3D pipeline 2422 is triggered via an execute 2434command or event. In some embodiments, a register write triggers commandexecution. In some embodiments execution is triggered via a ‘go’ or‘kick’ command in the command sequence. In one embodiment commandexecution is triggered using a pipeline synchronization command to flushthe command sequence through the graphics pipeline. The 3D pipeline willperform geometry processing for the 3D primitives. Once operations arecomplete, the resulting geometric objects are rasterized and the pixelengine colors the resulting pixels. Additional commands to control pixelshading and pixel back end operations may also be included for thoseoperations.

In some embodiments, the graphics processor command sequence 2410follows the media pipeline 2424 path when performing media operations.In general, the specific use and manner of programming for the mediapipeline 2424 depends on the media or compute operations to beperformed. Specific media decode operations may be offloaded to themedia pipeline during media decode. In some embodiments, the mediapipeline can also be bypassed and media decode can be performed in wholeor in part using resources provided by one or more general purposeprocessing cores. In one embodiment, the media pipeline also includeselements for general-purpose graphics processor unit (GPGPU) operations,where the graphics processor is used to perform SIMD vector operationsusing computational shader programs that are not explicitly related tothe rendering of graphics primitives.

In some embodiments, media pipeline 2424 is configured in a similarmanner as the 3D pipeline 2422. A set of media pipeline state commands2440 are dispatched or placed into in a command queue before the mediaobject commands 2442. In some embodiments, media pipeline state commands2440 include data to configure the media pipeline elements that will beused to process the media objects. This includes data to configure thevideo decode and video encode logic within the media pipeline, such asencode or decode format. In some embodiments, media pipeline statecommands 2440 also support the use one or more pointers to “indirect”state elements that contain a batch of state settings.

In some embodiments, media object commands 2442 supply pointers to mediaobjects for processing by the media pipeline. The media objects includememory buffers containing video data to be processed. In someembodiments, all media pipeline states must be valid before issuing amedia object command 2442. Once the pipeline state is configured andmedia object commands 2442 are queued, the media pipeline 2424 istriggered via an execute command 2444 or an equivalent execute event(e.g., register write). Output from media pipeline 2424 may then be postprocessed by operations provided by the 3D pipeline 2422 or the mediapipeline 2424. In some embodiments, GPGPU operations are configured andexecuted in a similar manner as media operations.

Graphics Software Architecture

FIG. 25 illustrates exemplary graphics software architecture for a dataprocessing system 2500 according to some embodiments. In someembodiments, software architecture includes a 3D graphics application2510, an operating system 2520, and at least one processor 2530. In someembodiments, processor 2530 includes a graphics processor 2532 and oneor more general-purpose processor core(s) 2534. The graphics application2510 and operating system 2520 each execute in the system memory 2550 ofthe data processing system.

In some embodiments, 3D graphics application 2510 contains one or moreshader programs including shader instructions 2512. The shader languageinstructions may be in a high-level shader language, such as the HighLevel Shader Language (HLSL) or the OpenGL Shader Language (GLSL). Theapplication also includes executable instructions 2514 in a machinelanguage suitable for execution by the general-purpose processor core2534. The application also includes graphics objects 2516 defined byvertex data.

In some embodiments, operating system 2520 is a Microsoft® Windows®operating system from the Microsoft Corporation, a proprietary UNIX-likeoperating system, or an open source UNIX-like operating system using avariant of the Linux kernel. When the Direct3D API is in use, theoperating system 2520 uses a front-end shader compiler 2524 to compileany shader instructions 2512 in HLSL into a lower-level shader language.The compilation may be a just-in-time (JIT) compilation or theapplication can perform shader pre-compilation. In some embodiments,high-level shaders are compiled into low-level shaders during thecompilation of the 3D graphics application 2510.

In some embodiments, user mode graphics driver 2526 contains a back-endshader compiler 2527 to convert the shader instructions 2512 into ahardware specific representation. When the OpenGL API is in use, shaderinstructions 2512 in the GLSL high-level language are passed to a usermode graphics driver 2526 for compilation. In some embodiments, usermode graphics driver 2526 uses operating system kernel mode functions2528 to communicate with a kernel mode graphics driver 2529. In someembodiments, kernel mode graphics driver 2529 communicates with graphicsprocessor 2532 to dispatch commands and instructions.

IP Core Implementations

One or more aspects of at least one embodiment may be implemented byrepresentative code stored on a machine-readable medium which representsand/or defines logic within an integrated circuit such as a processor.For example, the machine-readable medium may include instructions whichrepresent various logic within the processor. When read by a machine,the instructions may cause the machine to fabricate the logic to performthe techniques described herein. Such representations, known as “IPcores,” are reusable units of logic for an integrated circuit that maybe stored on a tangible, machine-readable medium as a hardware modelthat describes the structure of the integrated circuit. The hardwaremodel may be supplied to various customers or manufacturing facilities,which load the hardware model on fabrication machines that manufacturethe integrated circuit. The integrated circuit may be fabricated suchthat the circuit performs operations described in association with anyof the embodiments described herein.

FIG. 26 is a block diagram illustrating an IP core development system2600 that may be used to manufacture an integrated circuit to performoperations according to an embodiment. The IP core development system2600 may be used to generate modular, re-usable designs that can beincorporated into a larger design or used to construct an entireintegrated circuit (e.g., an SOC integrated circuit). A design facility2630 can generate a software simulation 2610 of an IP core design in ahigh level programming language (e.g., C/C++). The software simulation2610 can be used to design, test, and verify the behavior of the IPcore. A register transfer level (RTL) design can then be created orsynthesized from the simulation model 2600. The RTL design 2615 is anabstraction of the behavior of the integrated circuit that models theflow of digital signals between hardware registers, including theassociated logic performed using the modeled digital signals. Inaddition to an RTL design 2615, lower-level designs at the logic levelor transistor level may also be created, designed, or synthesized. Thus,the particular details of the initial design and simulation may vary.

The RTL design 2615 or equivalent may be further synthesized by thedesign facility into a hardware model 2620, which may be in a hardwaredescription language (HDL), or some other representation of physicaldesign data. The HDL may be further simulated or tested to verify the IPcore design. The IP core design can be stored for delivery to a 3^(rd)party fabrication facility 2665 using non-volatile memory 2640 (e.g.,hard disk, flash memory, or any non-volatile storage medium).Alternatively, the IP core design may be transmitted (e.g., via theInternet) over a wired connection 2650 or wireless connection 2660. Thefabrication facility 2665 may then fabricate an integrated circuit thatis based at least in part on the IP core design. The fabricatedintegrated circuit can be configured to perform operations in accordancewith at least one embodiment described herein.

FIG. 27 is a block diagram illustrating an exemplary system on a chipintegrated circuit 2700 that may be fabricated using one or more IPcores, according to an embodiment. The exemplary integrated circuitincludes one or more application processors 2705 (e.g., CPUs), at leastone graphics processor 2710, and may additionally include an imageprocessor 2715 and/or a video processor 2720, any of which may be amodular IP core from the same or multiple different design facilities.The integrated circuit includes peripheral or bus logic including a USBcontroller 2725, UART controller 2730, an SPI/SDIO controller 2735, andan I²S/I²C controller 2740. Additionally, the integrated circuit caninclude a display device 2745 coupled to one or more of ahigh-definition multimedia interface (HDMI) controller 2750 and a mobileindustry processor interface (MIPI) display interface 2755. Storage maybe provided by a flash memory subsystem 2760 including flash memory anda flash memory controller. Memory interface may be provided via a memorycontroller 2765 for access to SDRAM or SRAM memory devices. Someintegrated circuits additionally include an embedded security engine2770.

Additionally, other logic and circuits may be included in the processorof integrated circuit 2700, including additional graphicsprocessors/cores, peripheral interface controllers, or general purposeprocessor cores.

ADDITIONAL NOTES AND EXAMPLES

Example 1 may include a system for asynchronous display of a frame,comprising a computing device to determine changes between a currentframe and a previous frame, and an asynchronous display coupled to thecomputing device to display an image, wherein the computing device tosend frame updates asynchronously to the asynchronous display to onlyupdate areas of a currently displayed image that have changed.

Example 2 may include the system of Example 1, wherein each area of anew frame that is different from a corresponding area in the displayedimage is sent to the asynchronous display as a frame update along withcorresponding pixel address(es) to identify the location(s) of thearea(s) that has changed.

Example 3 may include the system of Example 1, wherein each area of anew frame that remains the same as the corresponding area in thedisplayed image is not sent to the asynchronous display.

Example 4 may include the system of Example 1, wherein areas of thedisplayed image that maintain their status in the new frame are notupdated or refreshed.

Example 5 may include the system of Example 1, wherein the computingdevice to determine the frame updates by comparing a new frame to berendered with the currently displayed image on the asynchronous displayand if an area has changed, the computing device to send the changedarea as a frame update along with a corresponding pixel address of thearea to identify the location of the area in the currently displayedimage that has changed.

Example 6 may include the system of Example 5, wherein the asynchronousdisplay to update the currently displayed image with the frame updatesreceived from the computing device in the locations identified by thecorresponding pixel addresses.

Example 7 may include the system of Example 1, wherein the computingdevice to send the updated frames to the display asynchronously ratherthan at a fixed frame rate.

Example 8 may include the system of Example 1, wherein the computingdevice includes at least one graphics processing unit (GPU), at leastone central processing unit (CPU), and a random access memory.

Example 9 may include a method for displaying pixels asynchronous,comprising of determining, by a computing device, changes in a new frameto be rendered on an asynchronous display, wherein the changes comprisepixels of a currently displayed image on the asynchronous display thathave changed in the new frame, wherein the changes represent updatedpixels and sending, by the computing device, the updated pixels alongwith corresponding pixel addresses representing the locations of theupdated pixels to enable the asynchronous display to update thecurrently displayed image with the updated pixels based on the pixeladdresses.

Example 10 may include the system of Example 9, wherein the updatedpixels and corresponding pixel addresses are sent to the asynchronousdisplay when they occur rather than at a fixed frame rate.

Example 11 may include the system of Example 9, wherein the updatedpixels and corresponding pixel addresses are sent asynchronously to theasynchronous display.

Example 12 may include at least one computer readable medium, comprisinga set of instructions, which when executed by a computing device causethe computing device to determine changes in a new frame to be renderedon an asynchronous display, wherein the changes comprise pixels of acurrently displayed image on the asynchronous display that have changedin the new frame, wherein the changes represent updated pixels, and sendthe updated pixels along with corresponding pixel addresses representingthe locations of the updated pixels to enable the asynchronous displayto update the currently displayed image with the updated pixels based onthe pixel addresses.

Example 13 may include at least one computer readable medium of Example12, wherein the updated pixels and corresponding pixel addresses aresent to the asynchronous display when they occur rather than at a fixedframe rate.

Example 14 may include at least one computer readable medium of Example12, wherein the updated pixels and corresponding pixel addresses aresent asynchronously to the asynchronous display.

Example 15 may include a system for block-based camera updates,comprising of a camera to capture an image n and determine pixel-basedblocks for the image n that are different from an image n−1 previouslycaptured by the camera, a system on a chip (SOC) coupled to a memorydevice and to the camera, the SOC to receive the updated pixel-basedblocks, retrieve the image n−1 from the memory device, merge the updatedpixel-based blocks with the image n−1 to obtain a merged image, andmodify a format of the merged image to a display format.

Example 16 may include the system of Example 15, further comprising adisplay coupled to the SOC, the display to receive the merged image anddisplay the merged image.

Example 17 may include the system of Example 15, wherein the camera todetermine pixel-based blocks for the image n is further to divide theimage n into small regions, determine a CRC for each small region,compare the CRC for each region of image n with a corresponding CRC foreach region of image n−1, if the CRC is different for a region, selectthat region as an updated region and tag the x,y coordinates for thatregion.

Example 18 may include a system for block-based camera updates,comprising of a camera to capture an image n and determine pixel-basedblocks and corresponding pixel addresses for the image n that aredifferent from an image n−1 previously captured by the camera, a systemon a chip (SOC) coupled to a memory device and to the camera, the SOC toreceive the updated pixel-based blocks and corresponding pixeladdresses, modify a format of the updated pixel-based blocks to adisplay format.

Example 19 may include the system of Example 18, further comprising amemory panel display coupled to the SOC, the memory panel display toreceive the updated pixel-based blocks in display format and thecorresponding pixel addresses from the SOC, retrieve the image n−1 fromthe memory panel display, merge the updated pixel-based blocks indisplay format with the image n−1 using the corresponding pixeladdresses to obtain a merged image, and display the merged image.

Example 20 may include the system of Example 18, wherein the camera todetermine pixel-based blocks for the image n is further to divide theimage n into small regions, determine a CRC for each small region,compare the CRC for each region of image n with a corresponding CRC foreach region of image n−1, if the CRC is different for a region, selectthat region as an updated region and tag the x,y coordinates for thatregion.

Example 21 may include a method for block-based camera updates,comprising of capturing, using a camera, an image n, determining whatregions of image n changed from the previous image n−1, merging thechanged regions with the previous image n−1 to obtain the new image n,and displaying the new image n.

Example 22 may include the system of Example 21, wherein determiningwhat regions of image n changed from the previous image n−1 comprisingof dividing the image n into small regions, determining a CRC for eachsmall region, comparing the CRC for each region of image n with acorresponding CRC for each region of image n−1, if the CRC is differentfor a region, selecting that region as an updated region and tagging x,ycoordinates for that region.

Example 23 may include the system of Example 22, wherein the x,ycoordinates define the location placement of the updated region in imagen−1.

Example 24 may include one or more computer readable mediums, comprisinga set of instructions, which when executed by one or more processorscause the processors to capture an image n, determine what regions ofimage n changed from the previous image n−1, merge the changed regionswith the previous image n−1 to obtain the new image n, and display thenew image n.

Example 25 may include one or more computer readable mediums of Example23, wherein instructions for determining what regions of image n changedfrom the previous image n−1 cause the processor to divide the image ninto small regions, determine a CRC for each small region, compare theCRC for each region of image n with a corresponding CRC for each regionof image n−1, and if the CRC is different for a region, select thatregion as an updated region and tag x,y coordinates for that region.

Example 26 may include one or more computer readable mediums of Example24, wherein the x,y coordinates define the location placement of theupdated region in image n−1.

Example 27 may include an asynchronous system for event driven updates,comprising of a computing system, a plurality of input devicescommunicatively coupled to the computing system, and at least one outputdevice, wherein upon an event occurring, based at least in part on oneinput device, the one input device to cause the at least one outputdevice to be asynchronously updated, wherein the update to only includechanges that have occurred since the previous update.

Example 28 may include the asynchronous system of Example 26, wherein atleast one of the plurality of input devices comprises an eye tracker totrack eye and head movements of a user of the computing system, whereinan event occurring based on the eye tracker to cause the output deviceto be updated at a time determined by the computing system.

Example 29 may include the asynchronous system of Example 26, wherein atleast one of the plurality of input devices comprises a differentialvideo camera to track the amount of light falling on each pixel in animage and when the light fluctuates up or down, the differential videocamera to send an event indicating the change in brightness to thecomputing system to cause the output device to be updated at a timedetermined by the computing system.

Example 30 may include the asynchronous system of Example 26, wherein atleast one of the plurality of input devices comprises a 6DOF tracker totrack a user's head position in six degrees of freedom, the 6DOF trackerto send an event indicating the change in head position in six degreesof freedom to the computing system to cause the output device to beupdated at a time determined by the computing system.

Example 31 may include the asynchronous system of Example 26, wherein atleast one of the plurality of input devices comprises a gesture trackerto track a user's hand movements to detect if a certain symbol or motionis made that is relevant to an action being performed on the computingsystem, the gesture tracker to send an event indicating a gesture to thecomputing system to cause the output device to be updated at a timedetermined by the computing system.

Example 32 may include the asynchronous system of claim 26, wherein atleast one of the plurality of input devices comprises a game controllerto track a user's inputs through knob and button selections, the gamecontroller to send an event indicating the user's input to the computingsystem to cause the output device to be updated at a time determined bythe computing system.

Example 33 may include the asynchronous system of any one of Examples26-32, wherein the output device comprises a display.

Example 34 may include the asynchronous system of any one of Examples26-32, wherein the output device to be updated at a time determined bythe computing system includes at least one display, wherein a scoringtable comprising relative weights for each input device is used by thecomputing system to determine when to render a new frame or block changeto the display.

Example 35 may include the asynchronous system of Example 34, whereineach input device is prioritized based on their relative weightsassigned from the scoring table.

Example 36 may include the asynchronous system of Example 26, whereinthe computing system comprises a gaming system and the plurality ofinputs include event driven cameras and sensors to asynchronously drivethe gaming system.

Example 37 may include the asynchronous system of Example 26, whereinthe at least one output device comprises a display, wherein when anevent occurs the computing system sends changes to the displayasynchronously.

Example 38 may include the asynchronous system of Example 37, whereinthe changes represent a change in pixels from a region of an image beingdisplayed and a pixel address associated with the change in pixels.

Example 39 may include a method for event driven frame updates on adisplay, the method comprising of waiting for an event or a timeoutcaused by one or more input devices to a computing system, uponreceiving the event or the timeout, adding a corresponding weightassociated with the event or timeout to a score, determining whether thescore exceeds a pre-defined limit for the event, if the score exceedsthe pre-defined limit, updating a frame, displaying the updated frameasynchronously, clearing the score, and returning to wait for the eventor timeout, if score does not exceed the pre-defined limit, returning towait for the event or timeout.

Example 40 may include the system of Example 39, wherein the one or moreinput devices include one or more of event driven cameras and sensors todrive an asynchronous gaming system.

Example 41 may include the system of Example 39, wherein the one or moreinput devices include one or more of an eye tracker, a differentialvideo camera, a 6DOF tracker, a gesture tracker, a game controller, andactions from one or more remote players over a network.

Example 42 may include the system of Example 39, wherein a timeoutperiodically occurs when an event requires a score update.

Example 43 may include the system of Example 39, wherein the pre-definedlimit comprises a maximum limit based on the event.

Example 44 may include at least one computer readable medium, comprisinga set of instructions, which when executed by a computing device causethe computing device to wait for an event or a timeout caused by one ormore input devices to a computing system, upon receipt of the event orthe timeout, add a corresponding weight associated with the event ortimeout to a score, determine whether the score exceeds a pre-definedlimit for the event, if the score exceeds the pre-defined limit, updatea frame, display the updated frame asynchronously, clear the score, andreturn to wait for the event or timeout, if the score does not exceedthe pre-defined limit, return to wait for the event or timeout.

Example 45 may include at least one computer readable medium of Example44, wherein the one or more input devices include one or more of eventdriven cameras and sensors to drive an asynchronous gaming system.

Example 46 may include at least one computer readable medium of Example44, wherein the one or more input devices include one or more of an eyetracker, a differential video camera, a 6DOF tracker, a gesture tracker,a game controller, and actions from one or more remote players over anetwork.

Example 47 may include at least one computer readable medium of Example44, wherein a timeout periodically occurs when an event requires a scoreupdate.

Example 48 may include at least one computer readable medium of Example44, wherein the pre-defined limit comprises a maximum limit based on theevent.

Example 49 may include a system for asynchronous display of a frame,comprising of means for determining changes between a current frame anda previous frame, means for sending the changes asynchronously to theasynchronous display to only update areas of a currently displayed imagethat have changed.

Example 50 may include the system of Example 49, wherein each area of anew frame that is different from a corresponding area in the displayedimage is sent to the asynchronous display as a frame update along withcorresponding pixel address(es) to identify the location(s) of thearea(s) that has changed.

Example 51 may include the system of Example 49, wherein each area of anew frame that remains the same as the corresponding area in thedisplayed image is not sent to the asynchronous display.

Example 52 may include the system of Example 49, wherein areas of thedisplayed image that maintain their status in the new frame are notupdated or refreshed.

Example 53 may include a system for block-based camera updates,comprising of means for capturing an image n, means for determiningupdated pixel-based blocks for the image n that are different from animage n−1 previously captured, means for merging the updated pixel-basedblocks with the image n−1 to obtain a merged image, and means formodifying a format of the merged image to a display format.

Example 54 may include the system of Example 53, further comprisingmeans for displaying the merged image.

Example 55 may include the system of Example 53, wherein means fordetermining updated pixel-based blocks further comprises means fordividing the image n into small regions, means for determining a CRC foreach small region, means for comparing the CRC for each region of imagen with a corresponding CRC for each region of image n−1, if the CRC isdifferent for a region, means for selecting that region as an updatedregion and means for tagging the x,y coordinates for that region.

Example 56 may include at least one computer readable medium, comprisinga set of instructions, which when executed by a computing system causethe computing system to carry out a method according to any one ofExamples 9-11.

Example 57 may include at least one computer readable medium, comprisinga set of instructions, which when executed by a computing system causethe computing system to carry out a method according to any one ofExamples 21-23.

Example 58 may include at least one computer readable medium, comprisinga set of instructions, which when executed by a computing system causethe computing system to carry out a method according to any one ofExamples 39-43.

The term “coupled” may be used herein to refer to any type ofrelationship, direct or indirect, between the components in question,and may apply to electrical, mechanical, fluid, optical,electromagnetic, electromechanical or other connections. In addition,the terms “first”, “second”, etc. may be used herein only to facilitatediscussion, and carry no particular temporal or chronologicalsignificance unless otherwise indicated. Additionally, it is understoodthat the indefinite articles “a” or “an” carries the meaning of “one ormore” or “at least one”.

As used in this application and in the claims, a list of items joined bythe term “one or more of” may mean any combination of the listed terms.For example, the phrases “one or more of A, B or C” may mean A, B, C; Aand B; A and C; B and C; or A, B and C.

The embodiments have been described above with reference to specificembodiments. Persons skilled in the art, however, will understand thatvarious modifications and changes may be made thereto without departingfrom the broader spirit and scope of the embodiments as set forth in theappended claims. The foregoing description and drawings are,accordingly, to be regarded in an illustrative rather than a restrictivesense.

What is claimed is:
 1. A system for asynchronous display of a frame,comprising: a computing device to determine changes between a currentframe and a previous frame; and an asynchronous display coupled to thecomputing device to display an image; wherein the computing device tosend frame updates asynchronously to the asynchronous display to onlyupdate areas of a currently displayed image that have changed.
 2. Thesystem of claim 1, wherein each area of a new frame that is differentfrom a corresponding area in the displayed image is sent to theasynchronous display as a frame update along with corresponding pixeladdress(es) to identify location(s) of the area(s) that has changed. 3.The system of claim 1, wherein areas of the displayed image thatmaintain their status in the new frame are not updated or refreshed. 4.The system of claim 1, wherein the computing device to determine theframe updates by comparing a new frame to be rendered with the currentlydisplayed image on the asynchronous display and if an area has changed,the computing device to send the changed area as a frame update alongwith a corresponding pixel address of the area to identify the locationof the area in the currently displayed image that has changed.
 5. Thesystem of claim 1, wherein the computing device to send the updatedframes to the display asynchronously rather than at a fixed frame rate.6. A method for displaying pixels asynchronously, comprising:determining, by a computing device, changes in a new frame to berendered on an asynchronous display, wherein the changes comprise pixelsof a currently displayed image on the asynchronous display that havechanged in the new frame, wherein the changes represent updated pixels;and sending asynchronously, by the computing device, the updated pixelsalong with corresponding pixel addresses representing the locations ofthe updated pixels to enable the asynchronous display to update thecurrently displayed image with the updated pixels based on the pixeladdresses.
 7. At least one computer readable medium, comprising a set ofinstructions, which when executed by a computing device cause thecomputing device to: determine changes in a new frame to be rendered onan asynchronous display, wherein the changes comprise pixels of acurrently displayed image on the asynchronous display that have changedin the new frame, wherein the changes represent updated pixels; and sendasynchronously the updated pixels along with corresponding pixeladdresses representing the locations of the updated pixels to enable theasynchronous display to update the currently displayed image with theupdated pixels based on the pixel addresses.
 8. A system for block-basedcamera updates, comprising: a camera to capture an image n and determinepixel-based blocks for the image n that are different from an image n−1previously captured by the camera; a system on a chip (SOC) coupled to amemory device and to the camera, the SOC to: receive the updatedpixel-based blocks; retrieve the image n−1 from the memory device; mergethe updated pixel-based blocks with the image n−1 to obtain a mergedimage; and modify a format of the merged image to a display format. 9.The system of claim 8, further comprising a display coupled to the SOC,the display to receive the merged image and display the merged image.10. A system for block-based camera updates, comprising: a camera tocapture an image n and determine pixel-based blocks and correspondingpixel addresses for the image n that are different from an image n−1previously captured by the camera; a system on a chip (SOC) coupled to amemory device and to the camera, the SOC to: receive the updatedpixel-based blocks and corresponding pixel addresses; modify a format ofthe updated pixel-based blocks to a display format.
 11. The system ofclaim 10, further comprising a memory panel display coupled to the SOC,the memory panel display to: receive the updated pixel-based blocks indisplay format and the corresponding pixel addresses from the SOC;retrieve the image n−1 from the memory panel display; merge the updatedpixel-based blocks in display format with the image n−1 using thecorresponding pixel addresses to obtain a merged image; and display themerged image.
 12. The system of claim 10, wherein the camera todetermine pixel-based blocks for the image n is further to: divide theimage n into small regions; determine a CRC for each small region;compare the CRC for each region of image n with a corresponding CRC foreach region of image n−1; if the CRC is different for a region, selectthat region as an updated region and tag the x,y coordinates for thatregion.
 13. A method for block-based camera updates, comprising:capturing, using a camera, an image n; determining what regions of imagen changed from the previous image n−1; merging the changed regions withthe previous image n−1 to obtain the new image n; and displaying the newimage n.
 14. The method of claim 13, wherein determining what regions ofimage n changed from the previous image n−1 comprises: dividing theimage n into small regions; determining a CRC (cyclic redundancy check)for each small region; comparing the CRC for each region of image n witha corresponding CRC for each region of image n−1; if the CRC isdifferent for a region, selecting that region as an updated region andtagging the x,y coordinates for that region.
 15. The method of claim 14,wherein the x,y coordinates define the location placement of the updatedregion in image n−1.
 16. One or more computer readable mediums,comprising a set of instructions, which when executed by one or moreprocessors cause the processors to: capture an image n; determine whatregions of image n changed from the previous image n−1; merge thechanged regions with the previous image n−1 to obtain the new image n;and display the new image n.
 17. An asynchronous system for event drivenupdates, comprising: a computing system; a plurality of input devicescommunicatively coupled to the computing system; and at least one outputdevice; wherein upon an event occurring, based at least in part on oneinput device, the one input device to cause the at least one outputdevice to be asynchronously updated, wherein the update to only includechanges that have occurred since the previous update.
 18. Theasynchronous system of claims 17, wherein the output device to beupdated at a time determined by the computing system includes at leastone display, wherein a scoring table comprising relative weights foreach input device is used by the computing system to determine when torender a new frame to the display.
 19. The asynchronous system of claim17, wherein the computing system comprises a gaming system and theplurality of inputs include event driven cameras and sensors toasynchronously drive the gaming system.
 20. A method for event drivenframe updates on a display, the method comprising: waiting for an eventor a timeout caused by one or more input devices to a computing system;upon receiving the event or the timeout, adding a corresponding weightassociated with the event or timeout to a score; determining whether thescore exceeds a pre-defined limit for the event; if the score exceedsthe pre-defined limit, updating a frame; displaying the updated frameasynchronously; clearing the score; and returning to wait for the eventor timeout; if the score does not exceed the pre-defined limit,returning to wait for the event or timeout.
 21. The method of claim 20,wherein the one or more input devices include one or more of eventdriven cameras and sensors to drive an asynchronous gaming system. 22.The method of claim 20, wherein a timeout periodically occurs when anevent requires a score update.
 23. The method of claim 20, wherein thepre-defined limit comprises a maximum limit based on the event.
 24. Atleast one computer readable medium, comprising a set of instructions,which when executed by a computing device cause the computing device to:wait for an event or a timeout caused by one or more input devices to acomputing system; upon receipt of the event or the timeout, add acorresponding weight associated with the event or timeout to a score;determine whether the score exceeds a pre-defined limit for the event;if the score exceeds the pre-defined limit, updating a frame; displayingthe updated frame asynchronously; clearing the score; and returning towait for the event or timeout; if the score does not exceed thepre-defined limit, returning to wait for the event or timeout.
 25. Theat least one computer readable medium of claim 28, wherein a timeoutperiodically occurs when an event requires a score update.